pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 24

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Table 1
Pin No.
G12
H12
Separate Analog Switches (only supported in BGA package)
B14
B1
N1
N14
Line Interface Receiver
A9
A8
Data Sheet
I/O Signals (cont’d)for P/PG-LBGA-160-1
Name
READY
DTACK
READY_EN
RLAS21
RLAS22
RLAS23
RLAS24
RL1.1
ROID1
RL2.1
Pin Type Buffer
O
O
I
IO
(analog)
IO
(analog)
IO
(analog)
IO
(analog)
I (analog) –
I
I (analog) –
Type
oD
(PU)
oD
(PU)
PD
–
–
–
–
–
24
Function
Data Ready
oD output only if activated by READY_EN = 1
Intel bus mode is selected. If not activated (READY_EN
= 0
Asynchronous handshake signal to indicate successful
read or write cycle.
Data Acknowledge
oD output only if activated by READY_EN = 1
motorola bus mode is selected. If not activated
(READY_EN = 0
Asynchronous handshake signal to indicate successful
read or write cycle.
Ready Enable
Activates the oD functionality of READY/ DTACK.
0
resistor is active). Pin READY/ DTACK can be
connected to VDD.
1
Analog Switch Connector port 1
Can be connected to VSSX if analog switch is not used
Analog Switch Connector port 2
Can be connected to VSSX if analog switch is not used
Analog Switch Connector port 3
Can be connected to VSSX if analog switch is not used
Analog Switch Connector port 4
Can be connected to VSSX if analog switch is not used
Line Receiver input 1, port 1
Analog input from the external transformer. Selected if
LIM1.DRS is cleared.
Receive Optical Interface Data, port 1
Unipolar data received from a fiber-optical interface with
2048 kbit/s (E1) or 1544 kbit/s (T1/J1). If CMI coding is
selected (MR0.RC(1:0) = ´01
internal DPLL recovers clock an data; no clock signal on
RCLKI2 is required.
Line Receiver input 2, port 1
Analog input from the external transformer. Selected if
LIM1.DRS is cleared.
B
B
: READY/ DTACK is not activated (only pull-up
: READY/ DTACK is an active oD output
B
) the pull-up resistor is active.
(HW compatibel to QuadFALC
(HW compatibel to QuadFALC
(HW compatibel to QuadFALC
(HW compatibel to QuadFALC
B
) the pull-up resistor is active.
b
´ and LIM0.DRS = ´1´), an
Rev. 1.3, 2006-01-25
®
®
®
®
v2.1)
v2.1)
v2.1)
v2.1)
Pin Descriptions
QuadLIU
PEF 22504
B
B
and if
and if
TM