pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 84

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Figure 23
3.7.1
For data input, two different data types are supported:
•
•
3.7.2
In E1 applications, HDB3 line code and AMI coding is provided for the data received from the ternary interface. In
T1/J1 mode, B8ZS and AMI code is supported. Selection of the receive line code is done with register bits
MR0.RC(1:0) (MR0). In case of the optical interface the CMI Code (1T2B) with HDB3 or AMI postprocessing is
provided. If CMI code is selected the receive route clock is recovered from the data stream. The CMI decoder does
not correct any errors. The HDB3 code is used along with double violation detection or extended code violation
detection (selectable by MR0.EXZE)). In AMI code all code violations are detected. The detected errors increment
the code violation counter (16 bits length).
The signal at the ternary interface is received at both ends of a transformer.
An overview of the receive line coding is given in
3.7.3
Each of the QuadLIU
Only for P/PG-LBGA-160-1 package it also includes an integrated analog switch, see
connectors RLAS2(1:4) must not be connected to VSSX. This allows the device to support 100
120
The 300
by LIM2.MPAS. So a simple software controlling of both switches is possible, independent from one another.
To enable switching of the separate analog switches of all four ports in general the register bits
GPC(3:6).ENMPAS must be all set to ´1´. This is an additional protection to avoid closing of the analog switches
if its connectors RLAS2(1:4) are connected to VSSX in fully QuadLIU
Data Sheet
Ternary coded signals received at pins RL1 and RL2 from 0 dB downto -43 dB for E1 or downto -36 dB for
T1/J1 ternary interface. The ternary interface is selected if LIM1.DRS is cleared.
Unipolar data (CMI code) on pin ROID received from an optical interface. The optical interface is selected if
LIM1.DRS is set and MR0.RC(1:0) = ´01
SYNC
E1 and 75
Recovered clock
selection
switch is controlled by the registerbit LIM0.RTRS (LIM0). The multi purpose analog switch is controlled
Recovered and Receive Clock Selection
Receive Line Interface
Receive Line Coding
Receive Line Interface
A
channel 1
C
E1 applications with a single bill of materials (so called “generic” modes).
TM
to
DCO_R
RCLK
receivers includes an integrated switchable resistor R
Recovered clock
selection
A
A: controlled by CMR5.DRSS(2:0)
B: controlled by GPC(2:4).RS(2:0)
channel 2
C
b
to
DCO_R
´.
RCLK
Table
Recovered clock
84
selection
13.
A
channel 3
C
to
DCO_R
RCLK
TM
Recovered clock
TERM
Version 1.2 hardware compatible
selection
A
QLIU _rec _c lk _s el_2
= 300
Figure
channel 4
C
Functional Description
to
DCO_R
RCLK
.
Rev. 1.3, 2006-01-25
Receive clock
selection
24. In this case the
B
QuadLIU
T1, 110
PEF 22504
pins
RCLK1
RCLK2
RCLK3
RCLK4
J1,
TM