pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 194
pef22504
Manufacturer Part Number
pef22504
Description
Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEF22504.pdf
(255 pages)
- Current page: 194 of 255
- Download datasheet (8Mb)
4.2.1
Receive Buffer Delay
RBD
Receive Buffer Delay
Field
RBD
Data Sheet
Status Registers
Bits
5:0
Type
r
Description
Receive Elastic Buffer Delay
These bits informs the user about the current delay (in time slots) through
the receive elastic buffer. The delay is updated every 512 or 256 bits
(DIC1.RBS(1:0)). Before reading this register the user has to set bit
DEC.DRBD in order to halt the current value of this register. After reading
RBD updating of this register is enabled. Not valid if the receive buffer is
bypassed.
000000
...
111111
B
B
B
Delay < 1 time slot
Delay > 63 time slot
Offset
xx49
194
H
Register DescriptionReceive Buffer Delay
Rev. 1.3, 2006-01-25
QuadLIU
PEF 22504
Reset Value
00
TM
H
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