pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 205
pef22504
Manufacturer Part Number
pef22504
Description
Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEF22504.pdf
(255 pages)
- Current page: 205 of 255
- Download datasheet (8Mb)
PRBS Bit Error Counter Lower Bytes
BECL
PRBS Bit Error Counter Lower Bytes
Field
BEC7
BEC6
BEC5
BEC4
BEC3
BEC2
BEC1
BEC0
Data Sheet
Bits
7
6
5
4
3
2
1
0
Type
r
r
r
r
r
r
r
r
Description
PRBS Bit Error Counter
If the PRBS monitor is enabled by LCR1.EPRM = ´1´ this 16-bit counter
is incremented with every received PRBS bit error in the PRBS
synchronous state LSR1.LLBAD = ´1´.
The error counter does not roll over.During alarm simulation, the counter
is incremented continuously with every second received bit. Clearing and
updating the counter is done according to bit MR1.ECM.If this bit is reset
the error counter is permanently updated in the buffer. For correct read
access of the PRBS bit error counter bit DEC.DBEC has to be set. With
the rising edge of this bit updating the buffer is stopped and the error
counter is reset.
Bit DEC.DBEC is automatically reset with reading the error counter high
byte. If MR1.ECM is set every second (interrupt ISR3.SEC) the error
counter is latched and then automatically reset. The latched error counter
state should be read within the next second.
Register DescriptionPRBS Bit Error Counter Lower Bytes
Offset
xx58
205
H
Rev. 1.3, 2006-01-25
QuadLIU
PEF 22504
Reset Value
00
TM
H
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