pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 248

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

7.6
The following table shows the necessary configuration for the Digital Clock Interface Mode (DCIM), see ITU-T
G.703 11/2001, chapter 13. The receive clock at RL1/RL2 (2.048 MHz) is supported at multi function port RPC.
The transmit clock at FCLKX (2.048 MHz) is transmitted at XL1/XL2.
DCIM mode is standardized only for 2.048 MHz (E1 mode, MR1.PMOD = ´0´). The QuadLIU
1.544 MHz if MR1.PMOD = ´1´.
Table 79
GPC6.COMP_DIS = ´1´
MR1.PMOD
LIM0.DCIM = ´1´
LIM1.RL = ´0´
CMR1.DXSS = ´0´
CMR1.DXJA = ´0´
LIM1.DRS = ´0´
MR0.RC(1:0) = ´10
MR0.XC(1:0) = ´10
PC1.RPC1(3:0) = ´1111
PC5.CRP = ´1´
CMR1.DRSS(1:0) or
CMR5.DRSS(2:0) : select the
appropriate channel
CMR1.DCS = ´1´
LIM0.MAS = ´0´
CMR1.RS(1:0) = ´10
CMR4.RS(2:0) = ´010
GCM(1:8) see
GCM6
LIM2.SCF, CMR6.SCFX,
CMR2.ECFAX, CMR2.ECFAR,
CMR3:CFAX(3:0), CMR3.CFAR(3:0),
CMR4.IAR(4:0), CMR5.IAX(4:0): see
Chapter 3.7.8
DIC1.RBS(1:0) = ´10
DIC1.XBS(1:0) = ´11
Data Sheet
Device Configuration for Digital Clock Interface Mode (DCIM)
Device Configuration for DCIM Mode
Chapter 3.5.5
and
b
b
Table 23
´
´
b
b
b
´ or
´
´
b
´
b
´
and
Sets the QuadLIU
Selects 2.048 MHz or 1.544 MHz, see text above
Selects DCIM mode.
TX clock mode.
Line interface mode RX
Line interface mode TX
Select RCLK as output
RX clock mode
Configure clock system
Configure DCO-X and DCO-R
Configure elastic buffers
248
TM
into a defined mode (necessary for proper operation)
Operational Description
Rev. 1.3, 2006-01-25
TM
can handle also
QuadLIU
PEF 22504
TM