m37905 Renesas Electronics Corporation., m37905 Datasheet - Page 123

• Manufacturer Part Number: m37905
• Description: Mitsubishi 16-bit Single-chip Microcomputer 7700 Family / 7900 Series
• Manufacturer: Renesas Electronics Corporation.

TIMER A
7.4 Event counter mode
Fig. 7.4.1 Structures of timer Ai register and timer Ai mode register in event counter mode
7-20
Timer Ai mode register (i = 0 to 4) (Addresses 56
Timer Ai mode register (i = 5 to 9) (Addresses D6
X : It may be either “0” or “1.”
Timer A0 register (Addresses 47
Timer A1 register (Addresses 49
Timer A2 register (Addresses 4B
Timer A3 register (Addresses 4D
Timer A4 register (Addresses 4F
Note: Reading from or writing to this register must be performed in a unit of 16 bits.
15 to 0
Bit
Bit
0
1
2
3
4
5
6
7
Any value in the range from “0000
Assuming that the set value = n, the counter divides the count source frequency by (n + 1)
during countdown, or by (FFFF
When reading, the register indicates the counter value.
Operating mode select bits
Pulse output function select bit
Count polarity select bit
Up-down switching factor select
bit
Fix this bit to “0” in event counter mode.
These bits are invalid in event counter mode.
Bit name
16
16
16
16
16
, 46
, 48
, 4E
, 4A
, 4C
16
7905 Group User’s Manual Rev.1.0
– n + 1) during countup.
16
16
16
16
16
16
)
)
b1 b0
0 1 : Event counter mode
0 : No pulse output (TAi
1 : Pulse output (TAi
0 : Counts at falling edge of external signal
1 : Counts at rising edge of external signal
0 : Contents of up-down register
1 : Input signal to TAi
)
)
)
” to “FFFF
programmable I/O port pin.)
output pin.)
Function
Timer A5 register (Addresses C7
Timer A6 register (Addresses C9
Timer A7 register (Addresses CB
Timer A8 register (Addresses CD
Timer A9 register (Addresses CF
16
16
16
(b15)
” can be set.
to 5A
to DA
b7
16
16
)
)
OUT
Function
OUT
pin
pin functions as a pulse
OUT
pin functions as a
(b8)
b0
b7 b6 b5 b4 b3 b2 b1 b0
b7
X X 0
16
16
16
16
16
, C6
, C8
, CE
, CA
, CC
16
16
16
16
16
Undefined
At reset
At reset
)
)
)
)
)
0
0
0
0
0
0
0
0
R/W
R/W
0 1
RW
RW
RW
RW
RW
RW
RW
RW
RW
b0