m37905 Renesas Electronics Corporation., m37905 Datasheet - Page 92

• Manufacturer Part Number: m37905
• Description: Mitsubishi 16-bit Single-chip Microcomputer 7700 Family / 7900 Series
• Manufacturer: Renesas Electronics Corporation.

level which is sent from the preceding comparator (X in Figure 6.5.2); the interrupt with the higher priority
level will be sent to the next comparator (Z in Figure 6.5.2). (The initial value of the comparison level is “0.”)
For an interrupt which is not requested, the comparison is not performed, and the priority level which is sent
from the preceding comparator is sent to the next comparator as it is. When the two priority levels are found
the same, as a resultant of the comparison, the priority level which is sent from the preceding comparator
will be sent to the next comparator. Accordingly, when the same priority level is set to multiple interrupts
by software, their interrupt priority levels are handled as follows:
> INT
receive > Timer B2 > Timer B1 > Timer B0 > Timer A4 > Timer A3 > Timer A2 > Timer A1 > Timer A0 >
INT
is detected by the above comparison.
this interrupt priority level is higher than IPL and the interrupt disable flag (I) is “0,” the interrupt request is
accepted. An interrupt request which is not accepted here is retained until it is accepted or its interrupt
request bit is cleared to “0” by software.
fetch cycle. However, when an op-code fetch cycle starts during detection of an interrupt priority, a new
interrupt priority detection does not start. (See Figure 6.6.2.) Since the state of the interrupt request bit and
interrupt priority levels are latched during the interrupt priority detection, even if they change, the interrupt
priority detection is performed for the state just before the change occurs.
no interrupt request is accepted until the CPU fetches the op code of the next instruction after the following
operation is completed:
The following explains the operation of the interrupt priority level detection circuit using Figure 6.5.2.
The interrupt priority level of a requested interrupt (Y in Figure 6.5.2) is compared with the resultant priority
UART2 transmit > UART2 receive > Timer A9 > Timer A8 > Timer A7 > Timer A6 > Timer A5 > INT
Among the multiple interrupt requests sampled at the same timing, one request with the highest priority level
Then, this highest interrupt priority level is compared with the processor interrupt priority level (IPL). When
The interrupt priority level is detected when the CPU fetches an op code, which is called the CPU’s op-code
The interrupt priority level is detected when the CPU fetches an op code. Therefore, in the following case,
•Execution of an instruction which requires many cycles, such as the MVN and MVP instructions
Fig. 6.5.2 Interrupt priority level detection model
2
> INT
5
> INT
Interrupt source Y
1
> INT
4
> INT
0
3
> A-D conversion > UART1 transmit > UART1 receive > UART0 transmit > UART0
Y
Z
X
7905 Group User’s Manual Rev.1.0
Comparator
(Priority level
comparison)
Time
6.5 Interrupt priority level detection circuit
X : Priority level sent from the preceding
Y : Priority level of interrupt source Y
Z : Highest priority level at this point
comparator (Highest priority level at this point)
When X
When X < Y then Z = Y
Y then Z = X
INTERRUPTS
7
> INT
6-11
6