m37905 Renesas Electronics Corporation., m37905 Datasheet - Page 264

• Manufacturer Part Number: m37905
• Description: Mitsubishi 16-bit Single-chip Microcomputer 7700 Family / 7900 Series
• Manufacturer: Renesas Electronics Corporation.

(1) Transmit enable bit (bit 0)
(2) Transmit buffer empty flag (bit 1)
(3) Receive enable bit (bit 2)
(4) Receive complete flag (bit 3)
(5) Overrun error flag (bit 4)
(6) Framing error flag, Parity error flag, Error sum flag (bits 5 to 7)
By setting this bit to “1,” UARTi enters the transmission-enabled state. By clearing this bit to “0”
during transmission, UARTi enters the transmission-disabled state after the transmission which was
in progress at that time is completed.
This flag is set to “1” when data set in the UARTi transmit buffer register has been transferred from
the UARTi transmit buffer register to the UARTi transmit register. This flag is cleared to “0” when data
has been set in the UARTi transmit buffer register.
By setting this bit to “1,” UARTi enters the reception-enabled state. By clearing this bit to “0” during
reception, UARTi quits the reception immediately and enters the reception-disabled state.
This flag is set to “1” when data has been ready in the UARTi receive register and that has been
transferred to the UARTi receive buffer register (i.e., when reception is completed). This flag is
cleared to “0” in one of the following cases:
• When the low-order byte of the UARTi receive buffer register has been read out
• When the receive enable bit (bit 2) has been cleared to “0”
Refer to section “11.3.7 Processing on detecting overrun error” and “11.4.7 Processing on
detecting error.”
Refer to section “11.4.7 Processing on detecting error.”
7905 Group User’s Manual Rev.1.0
11.2 Block description
SERIAL I/O
11-9