m37905 Renesas Electronics Corporation., m37905 Datasheet - Page 290

• Manufacturer Part Number: m37905
• Description: Mitsubishi 16-bit Single-chip Microcomputer 7700 Family / 7900 Series
• Manufacturer: Renesas Electronics Corporation.

11.3.7 Processing on detecting overrun error
In the clock synchronous serial I/O mode, an overrun error can be detected.
An overrun error occurs when the next data has been prepared in the UARTi receive register with the
receive complete flag = “1” (i.e. data is present in the UARTi receive buffer register) and next data is
transferred to the UARTi receive buffer register. In other words, an overrun error occurs when the next data
has been prepared before reading out the contents of the UARTi receive buffer register. When an overrun
error has occurred, the next receive data is written into the UARTi receive buffer register. Additionally,
when the receive error interrupt is selected (UARTi receive interrupt mode select bit = “1”), a UARTi receive
interrupt request occurs and its interrupt request bit is set to “1.” When the receive interrupt is selected
(UARTi receive interrupt mode select bit = “0”), the UARTi receive interrupt request bit does not change.
An overrun error is detected when data is transferred from the UARTi receive register to the UARTi receive
buffer register, and the overrun error flag is set to “1.” The overrun error flag is cleared to “0” by clearing
the receive enable bit to “0.”
When an overrun error occurs during reception, be sure to initialize the overrun error flag and UARTi
receive buffer register, and then perform reception again. When it is necessary to perform retransmission
owing to a receiver-side overrun error which has occurred during transmission, be sure to set the UARTi
transmit buffer register again, and start transmission again.
The methods of initializing the UARTi receive buffer register and that of setting the UARTi transmit buffer
register again are described below.
(1) Method of initializing UARTi receive buffer register
(2) Method of setting UARTi transmit buffer register again
Clear the receive enable bit to “0” (reception disabled).
Set the receive enable bit to “1” again (reception enabled).
Clear the serial I/O mode select bits to “000
Set the serial I/O mode select bits to “001
Set the transmit enable bit to “1” (transmission enabled), and set the transmit data to the UARTi
transmit buffer register.
7905 Group User’s Manual Rev.1.0
2
” again.
11.3 Clock synchronous serial I/O mode
2
” (serial I/O invalidated).
SERIAL I/O
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