m37905 Renesas Electronics Corporation., m37905 Datasheet - Page 325

• Manufacturer Part Number: m37905
• Description: Mitsubishi 16-bit Single-chip Microcomputer 7700 Family / 7900 Series
• Manufacturer: Renesas Electronics Corporation.

A-D CONVERTER
12.2 Block description
Fig. 12.2.9 Structure of A-D conversion interrupt control register
12-14
12.2.4 A-D conversion interrupt control register
Figure 12.2.9 shows the structure of the A-D conversion interrupt control register. For details about interrupts,
refer to “CHAPTER 6. INTERRUPTS.”
(1) Interrupt priority level select bits (bits 2 to 0)
(2) Interrupt request bit (bit 3)
Notes 1: Before using an A-D conversion interrupt, be sure to clear this bit to “0” by software.
A-D conversion interrupt control register (Address 70
interrupt, be sure to select one of the priority levels (1 to 7). When an A-D conversion interrupt
request occurs, its priority level is compared with the processor interrupt priority level (IPL). The
requested interrupt is enabled only when its priority level is higher than the IPL. (However, this
applies when the interrupt disable flag (I) = “0.”)
cleared to “0” when the A-D conversion interrupt request has accepted. This bit can be set to “1” or
cleared to “0” by software.
7 to 4
These bits are used to select an A-D conversion interrupt’s priority level. When using an A-D conversion
To disable an A-D conversion interrupt, set these bits to “000
This bit is set to “1” when an A-D conversion interrupt request has occurred. This bit is automatically
Bit
0
1
2
3
2: When writing to this bit, use the MOVM (MOVMB) or STA (STAB, STAD) instruction.
Interrupt priority level select bits
Interrupt request bit
Nothing is assigned.
Bit name
7905 Group User’s Manual Rev.1.0
0 : No interrupt requested
1 : Interrupt requested
b2 b1 b0
0 0 0 : Level 0 (Interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
16
)
Function
2
” (level 0).
b7 b6 b5 b4 b3 b2 b1 b0
Undefined
Undefined
At reset
(Note 1)
0
0
0
(Note 2)
R/W
RW
RW
RW
RW
—