m37905 Renesas Electronics Corporation., m37905 Datasheet - Page 282

• Manufacturer Part Number: m37905
• Description: Mitsubishi 16-bit Single-chip Microcomputer 7700 Family / 7900 Series
• Manufacturer: Renesas Electronics Corporation.

Fig. 11.3.5 Transmit operation
11.3.4 Transmit operation
When the transmit conditions described in section “11.3.3 Method of transmission” have been satisfied
in the case of an internal clock selected, a transfer clock is generated and the following operations are
automatically performed after 1 cycle of the transfer clock or less has passed. In the case of an external
clock selected, when the transmit conditions have been satisfied and then an external clock is input to the
CLK
•The UARTi transmit buffer register’s contents are transferred to the UARTi transmit register.
•The transmit buffer empty flag is set to “1.”
•The transmit register empty flag is cleared to “0.”
•8 transfer clocks are generated (in the case of an internal clock selected).
•A UARTi transmit interrupt request occurs, and the interrupt request bit is set to “1.”
The transmit operations are described below:
Valid edge : A falling edge is selected when the CLK polarity select bit = “0.”
Figure 11.3.5 shows the transmit operation.
When an internal clock is selected, if the transmit conditions for the next data are satisfied at completion
of the transmission, the transfer clock is generated continuously. Accordingly, when performing transmission
continuously, set the next transmit data to the UARTi transmit buffer register during transmission (when the
transmit register empty flag = “0”). When the transmit conditions for the next data are not satisfied, the
transfer clock stops at “H” level (when the CLK polarity select bit = “0”), or “L” level (when the CLK polarity
select bit = “1”).
Figures 11.3.6 and 11.3.7 show examples of transmit timing.
When 1-byte data has been transmitted, the transmit register empty flag is set to “1.” This indicates the
Data in the UARTi transmit register is transmitted from the TxD
This data is transmitted, bit by bit, sequentially beginning with the least significant bit.
of the clock output from or input to the CLK
completion of transmission.
i
pin, the following operations are automatically performed:
Note: This applies when the CLK polarity select bit = “0.”
Transfer clock output from
or input to the CLKi pin (Note)
When the CLK polarity select bit = “1,” data is shifted at the rising edge of the transfer clock.
A rising edge is selected when the CLK polarity select bit = “1.”
• •
•
UARTi transmit buffer register
UARTi transmit register
7905 Group User’s Manual Rev.1.0
i
pin.
11.3 Clock synchronous serial I/O mode
MSB
b7
D
7
D
D
6
7
D
D
D
Transmit data
6
5
7
i
pin synchronously with the valid edge
D
D
D
D
5
7
4
6
• •
•
D
D
D
D
4
6
3
5
D
D
D
D
2
3
4
5
D
D
D
D
2
4
1
3
LSB
D
D
D
D
b0
1
3
0
2
SERIAL I/O
D
D
D
D
0
1
2
7
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