m37905 Renesas Electronics Corporation., m37905 Datasheet - Page 68

• Manufacturer Part Number: m37905
• Description: Mitsubishi 16-bit Single-chip Microcomputer 7700 Family / 7900 Series
• Manufacturer: Renesas Electronics Corporation.

Notes 1: The PLL multiplication ratio select bits must be set so that f
Note: To set the peripheral device’s clock select bits 1, 0 to “01
Table 4.2.1 f
Table 4.2.2 Internal peripheral device’s operation clock frequency
device’s operation clock
(3) System clock select bit (bit 5)
(4) Peripheral device’s clock select bits 1, 0 (bits 7, 6)
System clock select bit
Internal peripheral
This bit selects a clock source of f
“1,” f
Clearing the PLL circuit operation enable bit (bit 1) to “0” clears the system clock select bit to “0.” Also,
while the PLL circuit operation enable bit = “0,” nothing can be written to the system clock select bit.
(Fixed to be “0.”)
In order to set the system clock select bit to “1” after reset, it is necessary to wait 2 ms after the
stabilization of f(X
To rewrite the PLL multiplication ratio select bits (bits 2 and 3), clear the system clock select bit to
“0” simultaneously. Then, set this bit to “1” 2 ms after the rewriting of the PLL multiplication ratio select
bits. (See Figure 4.2.3.)
These bits select the internal peripheral device’s operation clock frequency listed in Table 4.2.2.
2: Be sure that f
reset, these bits are allowed to be changed only once.
f
f
PLL
f
f
4096
f
f
512
16
64
(bit 5)
1
2
sys
as the one. (See Table 4.2.1.)
0
1
selection
sys
does not exceed 20 MHz.
IN
f
f
f
f
f
f
).
sys
sys
sys
sys
sys
sys
/2
/16
/64
/512
/4096
PLL circuit operation
00
enable bit (bit 1)
7905 Group User’s Manual Rev.1.0
sys
–
1
. When this bit = “0,” fX
f
f
f
f
f
f
Peripheral device’s clock select bits 1, 0
sys
sys
sys
sys
sys
sys
CLOCK GENERATING CIRCUIT
/8
/32
/256
/2048
01
PLL multiplication ratio select bits
2
,” be sure that a frequency of f
(bits 3, 2) (Note 1)
(Note)
11 (quadruple)
01 (double)
10 (triple)
sys
–
is in the range from 10 MHz to 20 MHz. After
f
f
f
f
f
f
IN
sys
sys
sys
sys
sys
sys
is selected as f
/2
/4
/32
/128
/1024
/8192
10
Clock source Frequency (Note 2)
sys
fX
f
f
f
sys
PLL
PLL
PLL
must be 10 MHz or less.
IN
; and when this bit =
Do not select.
f
sys
4.2 Clocks
f(X
f(X
f(X
11
f(X
IN
IN
IN
)
)
)
IN
)
2
3
4
4-7