m37905 Renesas Electronics Corporation., m37905 Datasheet - Page 67

• Manufacturer Part Number: m37905
• Description: Mitsubishi 16-bit Single-chip Microcomputer 7700 Family / 7900 Series
• Manufacturer: Renesas Electronics Corporation.

CLOCK GENERATING CIRCUIT
4.2 Clocks
Fig. 4.2.2 Structure of clock control register
4-6
4.2.2 Clock control register 0
Figure 4.2.2 shows the structure of the clock control register 0, and Figure 4.2.3 shows the setting procedure
for the clock control register 0 when using the PLL frequency multiplier.
(1) PLL circuit operation enable bit (bit 1)
(2) PLL multiplication ratio select bits (bits 2, 3)
Clock control register 0
Notes 1: Clear this bit to “0” if the PLL frequency multiplier needs not to be active.
Setting this bit to “1” enables the PLL frequency multiplier to be active and pin V
This bit = “1” while pin RESET = “L” level and after reset, so that, in this case, the PLL frequency
multiplier is active. Clear this bit to “0” if the PLL frequency multiplier need not to be active.
Note that, in the stop and flash memory parallel I/O modes, the PLL frequency multiplier is in active
and pin V
“19.4 Flash memory parallel I/O mode.”)
These bits select the multiplication ratio of the PLL frequency multiplier. (See Table 4.2.1.) To rewrite
these bits, clear the system clock select bit (bit 5) to “0” simultaneously. Then, set the system clock
select bit to “1” 2 ms after the rewriting of this bit. (See Figure 4.2.3.)
Note that, after reset, these bits are allowed to be changed only once.
Bit
0
1
2
3
4
5
6
7
2: Rewriting of these bits must be performed simultaneously with clearance of the system clock select bit (bit 5) to “0.” Then,
3: Clearance of the PLL circuit operation enable bit (bit 1) to “0” clears the system clock select bit to “0.” Also, while the PLL
In the stop and flash memory parallel I/O modes, the PLL frequency multiplier is inactive and pin V
less of the contents of this bit.
set bit 5 to “1” 2 ms after the rewriting of these bits. (After reset, these bits are allowed to be changed only once.)
circuit operation enable bit = “0,” nothing can be written to the system clock select bit. (Fixed to be “0.”)
Before setting of set the system clock select bit to “1” after reset, it is necessary to insert an interval of 2 ms after the
stabilization of f(X
Fix this bit to “1.”
PLL circuit operation enable bit
(Note 1)
PLL multiplication ratio select bits
(Note 2)
Fix this bit to “1.”
System clock select bit
Peripheral device’s clock select bit 0
Peripheral device’s clock select bit 1
CONT
is invalid regardless of the contents of this bit. (Refer to sections “15.3 Stop mode” and
Bit name
IN
).
(Address BC
(Note 3)
16
7905 Group User’s Manual Rev.1.0
)
0 : PLL frequency multiplier is inactive, and pin V
1 : PLL frequency multiplier is active, and pin V
b3 b2
0 0 : Do not select.
0 1 :
1 0 :
1 1 :
0 : fX
1 : f
See Table 4.2.2.
is invalid. (Floating)
PLL
IN
2
3
4
Function
CONT
b7 b6 b5 b4 b3 b2 b1 b0
is valid.
CONT
CONT
1
At reset
is invalid regard-
CONT
1
1
1
0
1
0
0
0
to be valid.
R/W
RW
RW
RW
RW
RW
RW
RW
RW
1