MPC8347 FREESCALE [Freescale Semiconductor, Inc], MPC8347 Datasheet - Page 100

• Manufacturer Part Number: MPC8347
• Description: Integrated Host Processor Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

System Design Information
21.3
Due to large address and data buses and high operating frequencies, the MPC8347EA can generate
transient power surges and high frequency noise in its power supply, especially while driving large
capacitive loads. This noise must be prevented from reaching other components in the MPC8347EA
system, and the MPC8347EA itself requires a clean, tightly regulated source of power. Therefore, the
system designer should place at least one decoupling capacitor at each V
of the MPC8347EA. These capacitors should receive their power from separate V
LV
placed directly under the device using a standard escape pattern. Others can surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, distribute several bulk storage capacitors around the PCB, feeding the V
and LV
have a low ESR (equivalent series resistance) rating to ensure the quick response time. They should also
be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk
capacitors are 100–330 µF (AVX TPS tantalum or Sanyo OSCON).
21.4
To ensure reliable operation, connect unused inputs to an appropriate signal level. Unused active low
inputs should be tied to OV
connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external V
the MPC8347EA.
21.5
The MPC8347EA drivers are characterized over process, voltage, and temperature. For all buses, the
driver is a push-pull single-ended driver type (open drain for I
To measure Z
or GND. Then the value of each resistor is varied until the pad voltage is OV
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and R
OV
other in value. Then, Z
100
DD
DD
, and GND power planes in the PCB, with short traces to minimize inductance. Capacitors can be
/2. R
DD
Decoupling Recommendations
Connection Recommendations
Output Buffer DC Impedance
planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should
P
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3
then becomes the resistance of the pull-up devices. R
0
for the single-ended drivers, an external resistor is connected from the chip pad to OV
0
= (R
DD
P
, GV
+ R
N
DD
)/2.
, or LV
DD
as required. Unused active high inputs should be
P
is trimmed until the voltage at the pad equals
DD
2
C).
, GV
P
and R
DD
DD
, LV
N
are designed to be close to each
, OV
DD
DD
, OV
DD
/2 (see
, GV
DD
DD
Freescale Semiconductor
DD
, OV
, and GND pins of
DD
Figure
, OV
, and LV
DD
DD
, GV
42). The
, GV
DD
DD
DD
,
pin
DD
,