MPC8347 FREESCALE [Freescale Semiconductor, Inc], MPC8347 Datasheet - Page 86

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MPC8347

Manufacturer Part Number
MPC8347
Description
Integrated Host Processor Hardware Specifications
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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Clocking
19.1
The system PLL is controlled by the RCWL[SPMF] parameter.
encodings for the system PLL.
As described in
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk).
and
CLKIN/PCI_SYNC_IN ratios.
86
Table 61
System PLL Configuration
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3
show the expected frequency values for the CSB frequency for select csb_clk to
Section 19,
“Clocking,” The LBIUCM, DDRCM, and SPMF parameters in the reset
Table 59. System PLL Multiplication Factors
RCWL[SPMF]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
System PLL Multiplication
Reserved
Table 59
Factor
× 16
× 10
× 11
× 12
× 13
× 14
× 15
× 2
× 3
× 4
× 5
× 6
× 7
× 8
× 9
shows the multiplication factor
Freescale Semiconductor
Table 60

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