MPC8347 FREESCALE [Freescale Semiconductor, Inc], MPC8347 Datasheet - Page 83

• Manufacturer Part Number: MPC8347
• Description: Integrated Host Processor Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

19 Clocking
Figure 40
The primary clock source can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device
is configured in PCI host or PCI agent mode. When the MPC8347EA is configured as a PCI host device,
CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷2) and the multiplexors for
PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input selects whether
CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICDn] parameters select
whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.
PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to
synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
with equal delay to all PCI agent devices in the system, to allow the MPC8347EA to function. When the
MPC8347EA is configured as a PCI agent device, PCI_CLK is the primary input clock and the CLKIN
signal should be tied to GND.
Freescale Semiconductor
CFG_CLKIN_DIV
shows the internal distribution of the clocks.
CLKIN
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3
MPC8347EA
System PLL
Figure 40. MPC8347EA Clock Subsystem
e300 core
PCI Clock
csb_clk
Clock
Divider
Unit
csb_clk to rest
of the device
ddr_clk
lbiu_clk
Core PLL
to local bus
memory
controller
to DDR
memory
controller
Clock
DDR
LBIU
/n
DLL
Div
/2
core_clk
6
6
5
LCLK[0:2]
LSYNC_OUT
LSYNC_IN
MCK[0:5]
MCK[0:5]
PCI_CLK_OUT[0:4]
PCI_CLK/
PCI_SYNC_IN
PCI_SYNC_OUT
DDR
Memory
Device
Local Bus
Memory
Device
Clocking
83