MPC8347 FREESCALE [Freescale Semiconductor, Inc], MPC8347 Datasheet - Page 102

• Manufacturer Part Number: MPC8347
• Description: Integrated Host Processor Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

System Design Information
the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed
for the output pins.
21.7
The MPC8347EA requires high resistance pull-up resistors (10 kΩ is recommended) on open-drain pins,
including I
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in
under normal operating conditions because most have asynchronous behavior, and spurious assertion
yields unpredictable results.
Refer to the PCI 2.3 specification for all pull-ups required for PCI.
21.8
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE Std. 1149.1 specification, but it is provided on all processors that implement the PowerPC
architecture. The MPC8347EA requires TRST to be asserted during reset conditions to ensure that the
JTAG boundary logic does not interfere with normal chip operation. While the TAP controller may be
forced to the reset state using only the TCK and TMS signals, systems typically assert TRST during
power-on reset. Because the JTAG interface is also used for accessing the common on-chip processor
(COP) function, simply tying TRST to PORESET is not practical.
The PowerPC COP function allows a remote computer system (typically, a PC with dedicated hardware
and debugging software) to access and control the internal operations of the processor. The COP interface
connects through the JTAG port of the processor, with some additional status monitoring signals. The COP
port requires the ability to assert TRST independently without causing PORESET. If the target system has
independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or
push-button switches, the COP reset signals must be merged into these signals with logic.
The arrangement shown in
ensuring that the target can drive HRESET as well. If the JTAG interface and COP header are not used,
TRST should be tied to PORESET so that it is asserted when the system reset signal (PORESET) is
asserted.
The COP header shown in
examination/modification, and other standard debugger features. It requires no more effort than adding an
unpopulated footprint for a header when needed. The COP interface has a standard header for connection
to the target system, based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg
header). There is no standardized way to number the header, shown in
different pin numbering schemes. Some headers are numbered top-to-bottom then left-to-right, others use
left-to-right then top-to-bottom, and still others number the pins counter clockwise from pin 1 (as with an
IC). Regardless of the numbering scheme, the signal placement recommended in
all known emulators.
102
Pull-Up Resistor Requirements
JTAG Configuration Signals
2
C pins, the Ethernet Management MDIO pin, and EPIC interrupt pins.
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3
Figure
43. Take care to ensure that these pins are maintained at a valid deasserted state
Figure 43
Figure 43
adds many benefits—breakpoints, watchpoints, register and memory
allows the COP to assert HRESET or TRST independently, while
Figure
43, so emulator vendors use
Figure 43
Freescale Semiconductor
is common to