MPC8347 FREESCALE [Freescale Semiconductor, Inc], MPC8347 Datasheet - Page 73

• Manufacturer Part Number: MPC8347
• Description: Integrated Host Processor Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Table 52
Freescale Semiconductor
MVREF1
MVREF2
NC
Notes:
1. This pin is an open-drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OV
2. This pin is an open-drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to OV
3. During reset, this output is actively driven rather than three-stated.
4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
5. This pin should have a weak pull-up if the chip is in PCI host mode. Follow the PCI specifications.
6. This pin must always be tied to GND
7. This pin must always be pulled up to OV
8. This pin must always be left not connected.
9. Thermal sensitive resistor.
10. It is recommended that MDIC0 be tied to GRD using an 18 Ω resistor and MDIC1 be tied to DDR power using an 18 Ω
PCI1_INTA/IRQ_OUT
PCI1_RESET_OUT
PCI1_AD[31:0]
PCI1_C/BE[3:0]
resistor.
provides the pin-out listing for the MPC8347EA, 620 PBGA package.
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3
Signal
Signal
Table 54. MPC8347EA (TBGA) Pinout Listing (continued)
Table 55. MPC8347EA (PBGA) Pinout Listing
DD
M3
AD2
W32, AA31, AA32, AA33, AA34, AB31,
AB32, AB33, AB34, AC29, AC31, AC33,
AC34, AD30, AD32, AD33, AD34, AE29,
AE30, AH32, AH33, AH34, AM33, AJ31,
AJ32, AJ33, AJ34, AK32, AK33, AK34,
AM34, AL33, AL34, AK31, AH30, AC32,
AE32, AH31, AL32, AG34, AE33, AF32,
AE34, AF34, AF33, AG33, AG32, AL11,
AM11, AP10, Y32, Y34, Y31, Y33
D20
B21
E19, D17, A16, A18, B17, B16, D16, B18,
E17, E16, A15, C16, D15, D14, C14, A12,
D12, B11, C11, E12, A10, C10, A9, E11,
E10, B9, B8, D9, A8, C9, D8, C8
A17, A14, A11, B10
No Connection
Package Pin Number
Package Pin Number
PCI
Pin Type
Pin Type
—
I
I
I/O
I/O
O
O
DD
Reference
Reference
DD
Supply
Voltage
Voltage
Power
DDR
DDR
.
—
Supply
Power
OV
OV
OV
OV
DD
DD
DD
DD
Notes
Notes
2
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