MPC8347 FREESCALE [Freescale Semiconductor, Inc], MPC8347 Datasheet - Page 15

• Manufacturer Part Number: MPC8347
• Description: Integrated Host Processor Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Table 10
Freescale Semiconductor
Input hold time for POR configuration signals with respect to
negation of HRESET
Time for the MPC8347EA to turn off POR configuration signals
with respect to the assertion of HRESET
Time for the MPC8347EA to turn on POR configuration signals
with respect to the negation of HRESET
Notes:
1. t
2. tCLKIN is the clock period of the input clock applied to CLKIN. It is valid only in PCI host mode. See the MPC8349EA
3. POR configuration signals consist of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
PLL lock times
DLL lock times
Notes:
1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio
2. The csb_clk is determined by the CLKIN and system PLL ratio. See
to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the MPC8349EA Integrated
Host Processor Reference Manual.
Integrated Host Processor Reference Manual.
results in the minimum and an 8:1 ratio results in the maximum.
PCI_SYNC_IN
MPC8347EA MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3
lists the PLL and DLL lock times.
is the clock period of the input clock applied to PCI_SYNC_IN. In PCI host mode, the primary clock is applied
Parameter/Condition
Table 9. RESET Initialization Timing Specifications (continued)
Table 10. PLL and DLL Lock Times
7680
Min
—
—
Section 19,
0
1
122,880
Max
100
“Clocking.”
—
—
4
csb_clk cycles
t
PCI_SYNC_IN
Unit
μs
ns
ns
RESET Initialization
Notes
1, 2
1, 3
3
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