MPC8347 FREESCALE [Freescale Semiconductor, Inc], MPC8347 Datasheet - Page 35

• Manufacturer Part Number: MPC8347
• Description: Integrated Host Processor Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

8.3.2
Table 33
Figure 15
Freescale Semiconductor
At recommended operating conditions with LV
MDC frequency
MDC period
MDC clock pulse width high
MDC to MDIO delay
MDIO to MDC setup time
MDIO to MDC hold time
MDC rise time
MDC fall time
Notes:
1. The symbols for timing specifications follow the pattern of t
2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the maximum frequency
3. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the delay is 70 ns and for
(reference)(state)
t
outputs (D) are invalid (X) or data hold time. Also, t
respect to the time data input signals (D) reach the valid state (V) relative to the t
to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter:
R (rise) or F (fall).
Parameter/Condition
is 8.3 MHz and the minimum frequency is 1.2 MHz; for a csb_clk of 375 MHz, the maximum frequency is
11.7 MHz and the minimum frequency is 1.7 MHz).
a csb_clk of 333 MHz, the delay is 58 ns).
MDKHDX
provides the MII management AC timing specifications.
shows the MII management AC timing diagram.
MII Management AC Electrical Specifications
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3
symbolizes management data timing (MD) for the time t
(Output)
(Input)
MDIO
MDIO
MDC
for inputs and t
Figure 15. MII Management Interface Timing Diagram
Table 33. MII Management AC Timing Specifications
Symbol
t
t
t
t
MDKHDX
MDDVKH
MDDXKH
(first two letters of functional block)(reference)(state)(signal)(state)
MDCH
t
t
t
f
t
MDCH
MDCR
MDHF
DD
MDC
MDC
t
is 3.3 V ± 10% or 2.5 V ± 5%
MDDVKH
t
1
MDC
t
MDKHDX
Min
32
10
—
—
—
—
5
0
MDDVKH
t
MDCF
(first two letters of functional block)(signal)(state)
symbolizes management data timing (MD) with
Typ
400
2.5
—
—
—
—
—
—
MDC
t
MDDXKH
from clock reference (K) high (H) until data
t
MDCR
Max
170
10
10
—
—
—
—
—
MDC
for outputs. For example,
clock reference (K) going
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
Notes
2
3
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