MPC8347 FREESCALE [Freescale Semiconductor, Inc], MPC8347 Datasheet - Page 19

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MPC8347

Manufacturer Part Number
MPC8347
Description
Integrated Host Processor Hardware Specifications
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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Table 18
6.2.2
Table 19
Freescale Semiconductor
At recommended operating conditions with GV
At recommended operating conditions with GV
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)
ADDR/CMD/MODT output setup with respect to MCK
ADDR/CMD/MODT output hold with respect to MCK
MCS(n) output setup with respect to MCK
Controller Skew for
MDQS—MDQ/MECC/MDM
Note:
1. t
2. This specification applies only to the DDR2 interface.
3. This specification applies only to the DDR interface.
bit that will be captured with MDQS[n]. This should be subtracted from the total timing budget.
CISKEW
provides the input AC timing specifications for the DDR SDRAM interface.
shows the DDR and DDR2 output AC timing specifications.
DDR and DDR2 SDRAM Output AC Timing Specifications
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3
represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding
Parameter
Parameter
Table 19. DDR and DDR2 SDRAM Output AC Timing Specifications
Table 18. DDR and DDR2 SDRAM Input AC Timing Specifications
400 MHz
333 MHz
266 MHz
200 MHz
DD
DD
of (1.8 V or 2.5 V) ± 5%.
of (1.8 V or 2.5 V) ± 5%.
Symbol
t
CISKEW
400 MHz
333 MHz
266 MHz
200 MHz
400 MHz
333 MHz
266 MHz
200 MHz
400 MHz
333 MHz
266 MHz
200 MHz
Symbol
t
t
t
DDKHCS
DDKHAS
DDKHAX
t
MCK
–600
–750
–750
–750
Min
1
1.95
2.40
3.15
4.20
1.95
2.40
3.15
4.20
1.95
2.40
3.15
4.20
Min
5
Max
600
750
750
750
Max
10
Unit
DDR and DDR2 SDRAM
ps
Unit
ns
ns
ns
ns
Notes
1
2
3
3
3
Notes
2
3
3
3
19

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