ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 24

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7854/ADE7858/ADE7868/ADE7878
POWER-UP PROCEDURE
The ADE7854/ADE7858/ADE7868/ADE7878 contain an on-
chip power supply monitor that supervises the power supply
(VDD). At power-up, until VDD reaches 2 V ± 10%, the chip is
in an inactive state. As VDD crosses this threshold, the power
supply monitor keeps the chip in this inactive state for an
additional 26 ms, allowing VDD to achieve 3.3 V − 10%, the
minimum recommended supply voltage. Because the PM0 and
PM1 pins have internal pull-up resistors and the external micro-
processor keeps them high, the ADE7854/ADE7858/ADE7868/
ADE7878 always power-up in sleep mode (PSM3). Then, an
external circuit (that is, a microprocessor) sets the PM1 pin to a
low level, allowing the ADE78xx to enter normal mode (PSM0).
The passage from PSM3 mode, in which most of the internal
circuitry is turned off, to PSM0 mode, in which all functionality
is enabled, is accomplished in less than 40 ms (see Figure 24 for
details).
If PSM0 mode is the only desired power mode, the PM1 pin can
be set low permanently by using a direct connection to ground.
The PM0 pin can remain open because the internal pull-up
resistor ensures that its state is high.
When the ADE7854/ADE7858/ADE7868/ADE7878 enter PSM0
mode, the I
used, then the SS /HSA pin must be toggled three times, high to
low. This action selects the SPI port for further use. If I
active serial port, Bit 1 (I2C_LOCK) of the CONFIG2 register
must be set to 1 to lock it in. From this moment, the ADE78xx
ignores spurious toggling of the SS /HSA pin, and an eventual
switch to use the SPI port is no longer possible. Likewise, if SPI
is the active serial port, any write to the CONFIG2 register locks
the port, at which time a switch to use the I
possible. Only a power-down or by setting the RESET pin low
can the ADE7854/ADE7858/ADE7868/ADE7878 be reset to use
the I
when the ADE78xx changes PSMx power modes.
Immediately after entering PSM0, the ADE7854/ADE7858/
ADE7868/ADE7878 set all registers to their default values,
including the CONFIG2 and LPOILVL registers.
2
C port. Once locked, the serial port choice is maintained
2
C port is the active serial port. If the SPI port is
POWERED UP
ADE78xx
0V
3.3V – 10%
2.0V ± 10%
TURNED ON
POR TIMER
2
C port is no longer
26ms
2
C is the
Figure 24. Power-Up Procedure
ENTER PSM3
Rev. D | Page 24 of 96
ADE78xx
MICROPROCESSOR
SETS ADE78xx
The ADE7854/ADE7858/ADE7868/ADE7878 signals the end of
the transition period by triggering the IRQ1 interrupt pin low and
setting Bit 15 (RSTDONE) in the STATUS1 register to 1. This
bit is 0 during the transition period and becomes 1 when the
transition ends. The status bit is cleared and the IRQ1 pin is
returned high by writing the STATUS1 register with the corres-
ponding bit set to 1. Because the RSTDONE is an unmaskable
interrupt, Bit 15 (RSTDONE) in the STATUS1 register must be
cancelled for the IRQ1 pin to return high. It is recommended to
wait until the IRQ1 pin goes low before accessing the STATUS1
register to test the state of the RSTDONE bit. At this point, as a
good programming practice, it is also recommended to cancel
all other status flags in the STATUS1 and STATUS0 registers by
writing the corresponding bits with 1.
Initially, the DSP is in idle mode, which means it does not
execute any instruction. This is the moment to initialize all
ADE78xx registers. The last register in the queue must be
written three times to ensure the register has been initialized.
Then, enable the data memory RAM protection and write
0x0001 into the run register to start the DSP (see the Digital
Signal Processor section for details on data memory RAM
protection and the run register).
If the supply voltage, VDD, drops lower than 2 V ± 10%, the
ADE7854/ADE7858/ADE7868/ADE7878 enter an inactive state,
which means that no measurements or computations are executed.
HARDWARE RESET
The ADE7854/ADE7858/ADE7868/ADE7878 each has a
RESET pin. If the ADE7854, ADE7858, ADE7868, or ADE7878
is in PSM0 mode and the RESET pin is set low, then the
ADE78xx enters the hardware reset state. The ADE78xx must
be in PSM0 mode for a hardware reset to be considered. Setting
the RESET pin low while the ADE78xx is in PSM1, PSM2, and
PSM3 modes does not have any effect.
If the ADE7854, ADE7858, ADE7868, or ADE7878 is in PSM0
mode and the RESET pin is toggled from high to low and then
back to high after at least 10 μs, all the registers are set to their
IN PSM0
40ms
TRIGGERED
INTERRUPT
RSTDONE
MICROPROCESSOR
MAKES THE
CHOICE BETWEEN
I
2
C AND SPI
PSM0 READY
ADE78xx