ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 85

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit
Location
14
15
Table 42. PHNOLOAD Register (Address 0xE608)
Bit
Location
0
1
2
3
4
5
6
7
8
15:9
Table 43. COMPMODE Register (Address 0xE60E)
Bit
Location
0
1
2
3
4
5
6
7
VSPHASE[2]
Reserved
NLPHASE[0]
NLPHASE[1]
NLPHASE[2]
FNLPHASE[0]
FNLPHASE[1]
FNLPHASE[2]
VANLPHASE[0]
VANLPHASE[1]
VANLPHASE[2]
Reserved
TERMSEL1[0]
TERMSEL1[1]
TERMSEL1[2]
TERMSEL2[0]
TERMSEL2[1]
TERMSEL2[2]
TERMSEL3[0]
TERMSEL3[1]
Bit Mnemonic
Bit Mnemonic
Bit Mnemonic
Default Value
0
0
Default Value
0
0
0
0
0
0
0
0
0
000 0000
Default Value
1
1
1
1
1
1
1
1
When this bit is set to 1, Phase C voltage generates Bit16 (SAG) in the STATUS1 register.
Reserved. This bit is always 0.
0: Phase A is out of no load condition based on total active/reactive powers.
0: Phase B is out of no load condition based on total active/reactive powers.
0: Phase C is out of no load condition based on total active/reactive powers.
0: Phase A is out of no load condition based on apparent power.
0: Phase B is out of no load condition based on apparent power.
0: Phase C is out of no load condition based on apparent power.
Reserved. These bits are always 0.
Phase B is included in the CF1 outputs calculations.
Phase C is included in the CF1 outputs calculations.
Phase B is included in the CF2 outputs calculations.
Phase C is included in the CF2 outputs calculations.
Phase B is included in the CF3 outputs calculations.
Description
Description
1: Phase A is in no load condition based on total active/reactive powers. Bit set together with
Bit 0 (NLOAD) in the STATUS1 register.
The ADE7854 no load condition is based only on the total active powers.
1: Phase B is in no load condition based on total active/reactive powers. Bit set together with
Bit 0 (NLOAD) in the STATUS1 register.
The ADE7854 no load condition is based only on the total active powers.
1: Phase C is in no load condition based on total active/reactive powers. Bit set together with
Bit 0 (NLOAD) in the STATUS1 register.
The ADE7854 no load condition is based only on the total active powers.
0: Phase A is out of no load condition based on fundamental active/reactive powers. This bit
is always 0 for ADE7854, ADE7858, and ADE7868.
1: Phase A is in no load condition based on fundamental active/reactive powers. This bit is
set together with Bit 1 (FNLOAD) in STATUS1.
0: Phase B is out of no load condition based on fundamental active/reactive powers. This bit
is always 0 for ADE7854, ADE7858, and ADE7868.
1: Phase B is in no load condition based on fundamental active/reactive powers. This bit is
set together with Bit 1 (FNLOAD) in STATUS1.
0: Phase C is out of no load condition based on fundamental active/reactive powers. This bit
is always 0 for ADE7854, ADE7858, and ADE7868.
1: Phase C is in no load condition based on fundamental active/reactive powers. This bit is
set together with Bit 1 (FNLOAD) in STATUS1.
1: Phase A is in no load condition based on apparent power. Bit set together with Bit 2
(VANLOAD) in the STATUS1 register.
1: Phase B is in no load condition based on apparent power. Bit set together with Bit 2
(VANLOAD) in the STATUS1 register.
1: Phase C is in no load condition based on apparent power. Bit set together with Bit 2
(VANLOAD) in the STATUS1 register.
Description
Setting all TERMSEL1[2:0] to 1 signifies the sum of all three phases is included in the CF1
output. Phase A is included in the CF1 outputs calculations.
Setting all TERMSEL2[2:0] to 1 signifies the sum of all three phases is included in the CF2
output. Phase A is included in the CF2 outputs calculations.
Setting all TERMSEL3[2:0] to 1 signifies the sum of all three phases is included in the CF3
output. Phase A is included in the CF3 outputs calculations.
Rev. D| Page 85 of 96
ADE7854/ADE7858/ADE7868/ADE7878