ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 32

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7854/ADE7858/ADE7868/ADE7878
POWER QUALITY MEASUREMENTS
Zero-Crossing Detection
The ADE7854/ADE7858/ADE7868/ADE7878 have a zero-
crossing (ZX) detection circuit on the phase current and voltage
channels. The neutral current datapath does not contain a zero-
crossing detection circuit. Zero-crossing events are used as a
time base for various power quality measurements and in the
calibration process.
The output of LPF1 is used to generate zero crossing events.
The low-pass filter is intended to eliminate all harmonics of
50 Hz and 60 Hz systems, and to help identify the zero-crossing
events on the fundamental components of both current and
voltage channels.
The digital filter has a pole at 80 Hz and is clocked at 256 kHz.
As a result, there is a phase lag between the analog input signal
(one of IA, IB, IC, VA, VB, and VC) and the output of LPF1.
The error in ZX detection is 0.0703° for 50 Hz systems (0.0843°
for 60 Hz systems). The phase lag response of LPF1 results in a
time delay of approximately 31.4° or 1.74 ms (at 50 Hz) between
its input and output. The overall delay between the zero crossing
on the analog inputs and ZX detection obtained after LPF1 is
about 39.6° or 2.2 ms (at 50 Hz). The ADC and HPF introduce
the additional delay. The LPF1 cannot be disabled to assure a
good resolution of the ZX detection. Figure 41 shows how the
zero-crossing signal is detected.
To provide further protection from noise, input signals to the
voltage channel with amplitude lower than 10% of full scale do
not generate zero-crossing events at all. The Current Channel ZX
detection circuit is active for all input signals independent of their
amplitudes.
The ADE7854/ADE7858/ADE7868/ADE7878 contain six zero-
crossing detection circuits, one for each phase voltage and
current channel. Each circuit drives one flag in the STATUS1
register. If a circuit placed in the Phase A voltage channel
detects one zero-crossing event, Bit 9 (ZXVA) in the STATUS1
register is set to 1.
Similarly, the Phase B voltage circuit drives Bit 10 (ZXVB), the
Phase C voltage circuit drives Bit 11 (ZXVC), and circuits placed
VA, VB, VC
IA, IB, IC,
OR
Figure 41. Zero-Crossing Detection on Voltage and Current Channels
PGA
REFERENCE
ADC
OR VA, VB, VC
IA, IB, IC,
xIGAIN[23:0] OR
xVGAIN[23:0]
DSP
0.855
0V
1
ZX
HPFDIS
[23:0]
39.6° OR 2.2ms @ 50Hz
HPF
ZX
ZX
LPF1
LPF1 OUTPUT
ZX
ZX
DETECTION
Rev. D | Page 32 of 96
in the current channel drive Bit 12 (ZXIA), Bit 13 (ZXIB), and
Bit 14 (ZXIC) in the STATUS1 register. If a ZX detection bit is
set in the MASK1 register, the IRQ1 interrupt pin is driven low
and the corresponding status flag is set to 1. The status bit is
cleared and the IRQ1 pin is set to high by writing to the STATUS1
register with the status bit set to 1.
Zero-Crossing Timeout
Every zero-crossing detection circuit has an associated timeout
register. This register is loaded with the value written into the
16-bit ZXTOUT register and is decremented (1 LSB) every
62.5 μs (16 kHz clock). The register is reset to the ZXTOUT
value every time a zero crossing is detected. The default value of
this register is 0xFFFF. If the timeout register decrements to 0
before a zero crossing is detected, one of Bits[8:3] of the
STATUS1 register is set to 1. Bit 3 (ZXTOVA), Bit 4 (ZXTOVB),
and Bit 5 (ZXTOVC) in the STATUS1 register refer to Phase A,
Phase B, and Phase C of the voltage channel; Bit 6 (ZXTOIA),
Bit 7 (ZXTOIB), and Bit 8 (ZXTOIC) in the STATUS1 register
refer to Phase A, Phase B, and Phase C of the current channel.
If a ZXTOIx or ZXTOVx bit is set in the MASK1 register, the
IRQ1 interrupt pin is driven low when the corresponding status bit
is set to 1. The status bit is cleared and the IRQ1 pin is returned to
high by writing to the STATUS1 register with the status bit set to 1.
The resolution of the ZXOUT register is 62.5 μs (16 kHz clock)
per LSB. Thus, the maximum timeout period for an interrupt is
4.096 sec: 2
Figure 42 shows the mechanism of the zero-crossing timeout
detection when the voltage or the current signal stays at a fixed
dc level for more than 62.5 μs × ZXTOUT μs.
Phase Sequence Detection
The ADE7854/ADE7858/ADE7868/ADE7878 have on-chip
phase sequence error detection circuits. This detection works
on phase voltages and considers only the zero crossings
STATUS1[31:0], x = V, A
IRQ1 INTERRUPT PIN
ZXZOxy FLAG IN
REGISTER VALUE
16-BIT INTERNAL
CURRENT
y = A, B, C
VOLTAGE
SIGNAL
OR
16
/16 kHz.
ZXTOUT
Figure 42. Zero-Crossing Timeout Detection
0V