ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 25

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

default values, including the CONFIG2 and LPOILVL registers.
The ADE78xx signals the end of the transition period by triggering
the IRQ1 interrupt pin low and setting Bit 15 (RSTDONE) in the
STATUS1 register to 1. This bit is 0 during the transition period
and becomes 1 when the transition ends. The status bit is cleared
and the IRQ1 pin is returned high by writing to the STATUS1
register with the corresponding bit set to 1.
After a hardware reset, the DSP is in idle mode, which means it
does not execute any instruction.
Because the I
ADE7858/ADE7868/ADE7878, it becomes active after a reset
state. If SPI is the port used by the external microprocessor, the
procedure to enable it must be repeated immediately after the
RESET pin is toggled back to high (see the
section for details).
At this point, it is recommended to initialize all of the ADE78xx
registers, enable data memory RAM protection, and then write
0x0001 into the run register to start the DSP. See the Digital
Signal Processor section for details on data memory RAM
protection and the run register.
2
C port is the default serial port of the ADE7854/
Serial Interfaces
Rev. D | Page 25 of 96
SOFTWARE RESET FUNCTIONALITY
Bit 7 (SWRST) in the CONFIG register manages the software
reset functionality in PSM0 mode. The default value of this bit is 0.
If this bit is set to 1, then the ADE7854/ADE7858/ADE7868/
ADE7878 enter the software reset state. In this state, almost all
internal registers are set to their default values. In addition, the
choice of which serial port, I
if the lock-in procedure has been executed previously (see the
Serial Interfaces for details). The registers that maintain their
values despite the SWRST bit being set to 1 are the CONFIG2
and LPOILVL registers. When the software reset ends, Bit 7
(SWRST) in the CONFIG register is cleared to 0, the IRQ1
interrupt pin is set low, and Bit 15 (RSTDONE) in the STATUS1
register is set to 1. This bit is 0 during the transition period and
becomes 1 when the transition ends. The status bit is cleared and
the IRQ1 pin is set back high by writing to the STATUS1 register
with the corresponding bit set to 1.
After a software reset ends, the DSP is in idle mode, which
means it does not execute any instruction. It is recommended
to initialize all the ADE7854/ADE7858/ADE7868/ADE7878
registers and then enable the data memory RAM protection and
write 0x0001 into the run register to start the DSP (see the
Digital Signal Processor section for details on data memory
RAM protection and the run register).
Software reset functionality is not available in PSM1, PSM2, or
PSM3 mode.
ADE7854/ADE7858/ADE7868/ADE7878
2
C or SPI, is in use remains unchanged