ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 84

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7854/ADE7858/ADE7868/ADE7878
Bit
Location
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
22:21
23
24
31:25
Table 41. PHSTATUS Register (Address 0xE600)
Bit
Location
2:0
3
4
5
8:6
9
10
11
12
13
Bit Mnemonic
ZXTOVC
ZXTOIA
ZXTOIB
ZXTOIC
ZXVA
ZXVB
ZXVC
ZXIA
ZXIB
ZXIC
RSTDONE
SAG
OI
OV
SEQERR
MISMTCH
Reserved
PKI
PKV
Reserved
Bit Mnemonic
Reserved
OIPHASE[0]
OIPHASE[1]
OIPHASE[2]
Reserved
OVPHASE[0]
OVPHASE[1]
OVPHASE[2]
VSPHASE[0]
VSPHASE[1]
Default Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
0
0
000 0000
Default Value
000
0
0
0
000
0
0
0
0
0
Description
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase C voltage is
missing.
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase A current is
missing.
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase B current is
missing.
When this bit is set to 1, it enables an interrupt when a zero crossing on Phase C current is
missing.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase A
voltage.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase B
voltage.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase C
voltage.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase A
current.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase B
current.
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on Phase C
current.
Because the RSTDONE interrupt cannot be disabled, this bit does not have any functionality
attached. It can be set to 1 or cleared to 0 without having any effect.
When this bit is set to 1, it enables an interrupt when a SAG event occurs on one of the
phases indicated by Bits[14:12] (VSPHASE[x]) in the PHSTATUS register (see Table 41).
When this bit is set to 1, it enables an interrupt when an overcurrent event occurs on one of
the phases indicated by Bits[5:3] (OIPHASE[x]) in the PHSTATUS register (see Table 41).
When this bit is set to 1, it enables an interrupt when an overvoltage event occurs on one of
the phases indicated by Bits[11:9] (OVPHASE[x]) in the PHSTATUS register (see Table 41).
When this bit is set to 1, it enables an interrupt when a negative-to-positive zero crossing on
Phase A voltage is not followed by a negative-to-positive zero crossing on Phase B voltage,
but by a negative-to-positive zero crossing on Phase C voltage.
When this bit is set to 1, it enables an interrupt when
greater than the value indicated in ISUMLVL register. Setting this bit to1 does not have any
consequence for ADE7854 and ADE7858.
Reserved. These bits do not manage any functionality.
When this bit is set to 1, it enables an interrupt when the period used to detect the peak
value in the current channel has ended.
When this bit is set to 1, it enables an interrupt when the period used to detect the peak
value in the voltage channel has ended.
Reserved. These bits do not manage any functionality.
Description
Reserved. These bits are always 0.
When this bit is set to 1, Phase A current generates Bit 17 (OI) in the STATUS1 register.
When this bit is set to 1, Phase B current generates Bit 17 (OI) in the STATUS1 register.
When this bit is set to 1, Phase C current generates Bit 17 (OI) in the STATUS1 register.
Reserved. These bits are always 0.
When this bit is set to 1, Phase A voltage generates Bit 18 (OV) in the STATUS1 register.
When this bit is set to 1, Phase B voltage generates Bit 18 (OV) in the STATUS1 register.
When this bit is set to 1, Phase C voltage generates Bit 18 (OV) in the STATUS1 register.
When this bit is set to 1, Phase A voltage generates Bit 16 (SAG) in the STATUS1 register.
When this bit is set to 1, Phase B voltage generates Bit 16 (SAG) in the STATUS1 register.
Rev. D| Page 84 of 96
ISUM
−
INWV
>
ISUMLVL
is