ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 65

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SEQUENCE
status register is read immediately to identify the phase that
triggered the interrupt. The name, PHx, in Figure 80 denotes
one of the PHSTATUS, IPEAK, VPEAK, or PHSIGN registers.
Then, STATUSx is written back to clear the status flag(s).
SERIAL INTERFACES
The ADE7854/ADE7858/ADE7868/ADE7878 have three serial
port interfaces: one fully licensed I
peripheral interface (SPI), and one high speed data capture port
(HSDC). As the SPI pins are multiplexed with some of the pins
of the I
gurations: one using the SPI port only and one using the I
port in conjunction with the HSDC port.
Serial Interface Choice
After reset, the HSDC port is always disabled. Choose between
the I
power-up or after a hardware reset. If the SS /HSA pin is kept
high, then the ADE7854/ADE7858/ADE7868/ADE7878 use the
I
pin is toggled high to low three times after power-up or after a
hardware reset, the ADE7854/ADE7858/ADE7868/ADE7878
use the SPI port until a new hardware reset is executed. This
manipulation of the SS /HSA pin can be accomplished in two
ways. First, use the SS /HSA pin of the master device (that is, the
microcontroller) as a regular I/O pin and toggle it three times.
Second, execute three SPI write operations to a location in the
address space that is not allocated to a specific ADE78xx register
(for example 0xEBFF, where eight bit writes can be executed).
These writes allow the SS /HSA pin to toggle three times. See the
SPI Write Operation
involved.
After the serial port choice is completed, it needs to be locked.
Consequently, the active port remains in use until a hardware
reset is executed in PSM0 normal mode or until a power-down.
If I
PROGRAM
2
C port until a new hardware reset is executed. If the SS /HSA
2
C is the active serial port, Bit 1 (I2C_LOCK) of the CONFIG2
2
C and SPI ports by manipulating the SS /HSA pin after
IRQx
2
SEQUENCE
PROGRAM
C and HSDC ports, the ADE78xx accepts two confi-
t
IRQx
1
TO ISR
JUMP
t
1
section for details on the write protocol
INTERRUPT
TO ISR
JUMP
GLOBAL
MASK
Figure 80. Interrupt Management when PHSTATUS, IPEAK, VPEAK, or PHSIGN Registers are Involved
INTERRUPT
GLOBAL
MASK
CLEAR MCU
INTERRUPT
2
FLAG
C interface, one serial
CLEAR MCU
INTERRUPT
FLAG
STATUSx
READ
STATUSx
READ
STATUSx
WRITE
BACK
Figure 79. Interrupt Management
2
t
C
2
Rev. D | Page 65 of 96
READ
PHx
(BASED ON STATUSx CONTENTS)
STATUSx
WRITE
BACK
ISR ACTION
t
register must be set to 1 to lock it in. From this moment, the
ADE7854/ADE7858/ADE7868/ADE7878 ignore spurious
toggling of the SS pin and an eventual switch into using the SPI
port is no longer possible. If the SPI is the active serial port, any
write to the CONFIG2 register locks the port. From this moment,
a switch into using the I
the serial port choice is maintained when the ADE78xx changes
PSMx power modes.
The functionality of the ADE78xx is accessible via several on-
chip registers. The contents of these registers can be updated or
read using either the I
the state of up to 16 registers representing instantaneous values of
phase voltages and neutral currents, and active, reactive, and
apparent powers.
I
The ADE7854/ADE7858/ADE7868/ADE7878 supports a fully
licensed I
hardware slave. SDA is the data I/O pin, and SCL is the serial
clock. These two pins are shared with the MOSI and SCLK pins
of the on-chip SPI interface. The maximum serial clock frequency
supported by this interface is 400 kHz.
The two pins used for data transfer, SDA and SCL, are confi-
gured in a wire-AND’ e d format that allows arbitration in a
multimaster system.
The transfer sequence of an I
initiating a transfer by generating a start condition while the bus
is idle. The master transmits the address of the slave device and
the direction of the data transfer in the initial address transfer. If
the slave acknowledges, the data transfer is initiated. This con-
tinues until the master issues a stop condition, and the bus
becomes idle.
2
2
C-Compatible Interface
t
ADE7854/ADE7858/ADE7868/ADE7878
3
(BASED ON STATUSx CONTENTS)
2
C interface. The I
ISR ACTION
MCU
INTERRUPT
FLAG SET
GLOBAL INTERRUPT
MASK RESET
ISR RETURN
t
3
2
C or SPI interfaces. The HSDC port provides
2
C port is no longer possible. Once locked,
2
2
MCU
INTERRUPT
FLAG SET
C interface is implemented as a full
C system consists of a master device
GLOBAL INTERRUPT
TO ISR
JUMP
MASK RESET
ISR RETURN
TO ISR
JUMP