ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 53

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Integration Time Under A Steady Load
The discrete time sample period (T) for the accumulation register
is 125 μs (8 kHz frequency). With full-scale pure sinusoidal signals
on the analog inputs and a 90° phase difference between the vol-
tage and the current signal (the largest possible reactive power),
the average word value representing the reactive power is PMAX =
33,516,139 = 0x1FF6A6B. If the VARTHR threshold is set at the
PMAX level, this means the DSP generates a pulse that is added
at the var-hour registers every 125 μs.
The maximum value that can be stored in the var-hour
accumulation register before it overflows is 2
0x7FFFFFFF. The integration time is calculated as
Energy Accumulation Modes
The reactive power accumulated in each var-hour accumulation
32-bit register (AVARHR, BVARHR, CVARHR, AFVARHR,
BFVARHR, and CFVARHR) depends on the configuration of
Bits[5:4] (CONSEL[1:0]) in the ACCMODE register, in correlation
with the watt-hour registers. The different configurations are
described in Table 19. Note that IA ’ /IB ’ /IC ’ are the phase-shifted
current waveforms.
Table 19. Inputs to Var-Hour Accumulation Registers
CONSEL[1:0]
00
01
10
11
Bits[3:2] (VARACC[1:0]) in the ACCMODE register determine
how CF frequency output can be a generated function of the total
active and fundamental powers. While the var-hour accumulation
registers accumulate the reactive power in a signed format, the
frequency output can be generated in either the signed mode or the
sign adjusted mode function of VARACC[1:0]. See the Energy-to-
Frequency Conversion section for details.
Line Cycle Reactive Energy Accumulation Mode
As mentioned in the Line Cycle Active Energy Accumulation
Mode section, in line cycle energy accumulation mode, the
energy accumulation can be synchronized to the voltage
channel zero crossings so that reactive energy can be accu-
mulated over an integral number of half line cycles.
Time = 0x7FFF,FFFF × 125 μs = 74 hr 33 min 55 sec
AVARHR,
AFVARHR
VA × IA’
VA × IA’
VA × IA’
VA × IA’
BVARHR,
BFVARHR
VB × IB’
0
VB × IB’
VB = −VA − VC
VB × IB’
VB = −VA
31
− 1 or
CVARHR,
CFVARHR
VC × IC’
VC × IC’
VC × IC’
VC × IC’
(38)
Rev. D | Page 53 of 96
In this mode, the ADE7858/ADE7868/ADE7878 transfer the
reactive energy accumulated in the 32-bit internal accumulation
registers into the xVARHR or xFVARHR registers after an
integral number of line cycles, as shown in Figure 67. The
number of half line cycles is specified in the LINECYC register.
The line cycle reactive energy accumulation mode is activated by
setting Bit 1 (LVAR) in the LCYCMODE register. The total reactive
energy accumulated over an integer number of half line cycles
or zero crossings is available in the var-hour accumulation registers
after the number of zero crossings specified in the LINECYC reg-
ister is detected. When using the line cycle accumulation mode,
Bit 6 (RSTREAD) of the LCYCMODE register should be set to
Logic 0 because a read with the reset of var-hour registers is not
available in this mode.
Phase A, Phase B, and Phase C zero crossings are, respectively,
included when counting the number of half line cycles by setting
Bits[5:3] (ZXSEL[x]) in the LCYCMODE register. Any combi-
nation of the zero crossings from all three phases can be used
for counting the zero crossing. Select only one phase at a time
for inclusion in the zero-crossings count during calibration.
For details on setting the LINECYC register and the Bit 5
(LENERGY) in the MASK0 interrupt mask register associated
with the line cycle accumulation mode, see the Line Cycle
Active Energy Accumulation Mode section.
ALGORITHM
REACTIVE
OUTPUT
POWER
TOTAL
FROM
DETECTION
DETECTION
DETECTION
ADE7854/ADE7858/ADE7868/ADE7878
CROSSING
CROSSING
CROSSING
(PHASE A)
(PHASE B)
(PHASE C)
ZERO-
ZERO-
ZERO-
AVARGAIN
Figure 67. Line Cycle Reactive Energy Accumulation Mode
LCYCMODE[7:0]
LCYCMODE[7:0]
LCYCMODE[7:0]
ZXSEL[0] IN
ZXSEL[1] IN
ZXSEL[2] IN
AVAROS
ACCUMULATOR
VARTHR[47:0]
LINECYC[15:0]
CALIBRATION
CONTROL
AVARHR[31:0]
REGISTER
32-BIT