TV04A640JB-G Comchip Technology, TV04A640JB-G Datasheet - Page 25

• Manufacturer Part Number: TV04A640JB-G
• Description: TVS 400W 64V BIDIRECT SMA
• Manufacturer: Comchip Technology

Specifications of TV04A640JB-G

• Voltage - Reverse Standoff (typ): 64V
• Voltage - Breakdown: 71.1V
• Power (watts): 400W
• Polarization: Bidirectional
• Mounting Type: Surface Mount
• Package / Case: DO-214AC, SMA
• Channels: 1 Channel
• Clamping Voltage: 103 V
• Operating Voltage: 3.5 V
• Breakdown Voltage: 71.1 V
• Peak Surge Current: 40 A
• Peak Pulse Power Dissipation: 400 W
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.5
September 8, 2009 S25FL128P_00_08
11.4.2
Write Enable (WREN: 06h)
Parallel Mode
The maximum clock frequency allowed on the SCK input pin in parallel mode is 10 MHz. The Parallel Mode
Entry command (55h) must be issued before writing the READ_ID command. Once in the parallel mode, the
flash memory will not exit parallel mode until a Parallel Mode Exit (45h) command is given to the flash device,
or upon power-down/power-up sequence.
The Write Enable (WREN) command (see
enables the device to accept a Write Status Register, program, or erase command. The WEL bit must be set
prior to every Page Program (PP), Erase (SE or BE) and Write Status Register (WRSR) command.
The host system must first drive CS# low, write the WREN command, and then drive CS# high.
PO[7-0]
SCK
CS#
SI
Device Identification (Memory Capacity)
SO/PO[7-0]
Manufacturer Identification
0
SCK
CS#
1
Description
D a t a
SI
Figure 11.8 Write Enable (WREN) Command Sequence
2
High Impedance
Figure 11.7 Parallel Read_ID Instruction Sequence
Instruction
Mode 3
Mode 0
Hi-Z
90h
3
Table 11.2 READ_ID Command and Data
4
S h e e t
5
0 1 2 3 4 5 6 7
S25FL128P
6
Figure
7
MSB
15
8
Command
14
11.8) sets the Write Enable Latch (WEL) bit to a 1, which
9
13
1
2 Dummy
0
Bytes
2
3
0
2
2
1
22
1
Address
00000h
00001h
2
0
3
7
2
4
6
2
5
5
2
6
ADD (1)
Manufacture ID
4
2
7
3
2
8
Device ID
2
2
9
1
3
0
Data
01h
17h
0
3
1
Byte
1
3
2
Byte
2
3
3
3
25
4