TV04A640JB-G Comchip Technology, TV04A640JB-G Datasheet - Page 33

• Manufacturer Part Number: TV04A640JB-G
• Description: TVS 400W 64V BIDIRECT SMA
• Manufacturer: Comchip Technology

Specifications of TV04A640JB-G

• Voltage - Reverse Standoff (typ): 64V
• Voltage - Breakdown: 71.1V
• Power (watts): 400W
• Polarization: Bidirectional
• Mounting Type: Surface Mount
• Package / Case: DO-214AC, SMA
• Channels: 1 Channel
• Clamping Voltage: 103 V
• Operating Voltage: 3.5 V
• Breakdown Voltage: 71.1 V
• Peak Surge Current: 40 A
• Peak Pulse Power Dissipation: 400 W
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.10 Sector Erase (SE: 20h, D8h)
September 8, 2009 S25FL128P_00_08
The Sector Erase (SE) command sets all bits at all addresses within a specified sector to a logic 1. A WREN
command is required prior to writing the SE command.
The host system must drive CS# low, and then write the SE command plus three address bytes on SI. Any
address within the sector (see
driven low for the entire duration of the SE sequence. The command sequence is shown in
Table
The host system must drive CS# high after the device has latched the 24th bit of the Address input, otherwise
the device does not execute the command. The SE operation begins as soon as CS# is driven high. The
device internally controls the timing of the operation, which requires a period of t
be read to check the value of the Write In Progress (WIP) bit while the SE operation is in progress. The WIP
bit is 1 during the SE operation, and is 0 when the operation is completed. The device internally resets the
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).
The device does not execute an SE command that specifies a sector that is protected by the Block Protect
bits (see
SO/PO[7-0]
11.6.
CS#
SCK
Table 7.1 on page
SI
Hi-Z
Mode 3
Mode 0
D a t a
Figure 11.16 Sector Erase (SE) Command Sequence
13).
0
Table 7.1 on page
1
S h e e t
2
Command
S25FL128P
3
4
13) is a valid address for the SE command. CS# must be
5
6
7
MSB
23 22
8
9
24-bit Address
21
10
28
3
29
SE
2
. The Status Register may
30
1
31
0
Figure 11.16
and
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