DSPIC33FJ12MC201-I/SO Microchip Technology, DSPIC33FJ12MC201-I/SO Datasheet - Page 149

• Manufacturer Part Number: DSPIC33FJ12MC201-I/SO
• Description: IC DSPIC MCU/DSP 12K 20SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ12MC201-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 12KB (12K x 8)
• Package / Case: 20-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 15
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 15
• Data Ram Size: 1 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.3.4
In Double Update mode (PTMOD<1:0> = 11), an inter-
rupt event is generated each time the P
is equal to zero, as well as each time a period match
occurs. The postscaler selection bits have no effect in
this mode of the timer.
Double Update mode provides two additional functions:
• The control loop bandwidth is doubled because
• Asymmetrical center-aligned PWM waveforms can
14.3.5
The input clock to P
options of 1:1, 1:4, 1:16 or 1:64, selected by control bits
PTCKPS<1:0> in the P
counter is cleared when any of the following occur:
• A write to the P
• A write to the P
• Any device Reset
The P
written.
14.3.6
The match output of P
scaled through a 4-bit postscaler (which gives a 1:1 to
1:16 scaling).
The postscaler counter is cleared when any of the
following occur:
• A write to the P
• A write to the P
• Any device Reset
The P
written.
© 2007 Microchip Technology Inc.
the PWM duty cycles can be updated twice per
period.
be generated, which can be useful for minimizing
output waveform distortion in certain motor control
applications.
Note:
X
X
TMR register is not cleared when P
TMR register is not cleared when P
DOUBLE UPDATE MODE
Programming a value of 0x0001 in the
PWM Period register could generate a
continuous interrupt pulse and must be
avoided.
PWM TIME BASE PRESCALER
PWM TIME BASE POSTSCALER
X
X
X
X
TMR register
TCON register
TMR register
TCON register
X
X
TMR (F
X
TMR can optionally be post-
TCON SFR. The prescaler
OSC
/4) has prescaler
X
X
TMR register
TCON is
X
TCON is
Preliminary
dsPIC33FJ12MC201/202
14.4
P
period for the PWM time base. P
buffered register. The P
loaded into the P
• Free-Running and Single-Shot modes: When the
• Up/Down Count modes: When the PxTMR
The value held in the PxTPER buffer is automatically
loaded into the PxTPER register when the PWM time
base is disabled (PTEN = 0).
The
Equation 14-1:
EQUATION 14-1:
If the PWM time base is configured for one of the Up/
Down Count modes, the PWM period will be twice the
value provided by Equation 14-1.
The maximum resolution (in bits) for a given device
oscillator and PWM frequency can be determined using
Equation 14-2:
EQUATION 14-2:
14.5
Edge-aligned PWM signals are produced by the module
when the PWM time base is in Free-Running or Single-
Shot mode. For edge-aligned PWM outputs, the output
has a period specified by the value in PxTPER and a
duty cycle specified by the appropriate Duty Cycle reg-
ister (see Figure 14-3). The PWM output is driven active
at the beginning of the period (PxTMR = 0) and is driven
inactive when the value in the Duty Cycle register
matches PxTMR.
If the value in a particular Duty Cycle register is zero,
the output on the corresponding PWM pin is inactive
for the entire PWM period. In addition, the output on
the PWM pin is active for the entire PWM period if the
value in the Duty Cycle register is greater than the
value held in the PxTPER register.
T
X
P
the PxTPER register.
register is zero.
TPER is a 15-bit register used to set the counting
PWM
X
TMR register is reset to zero after a match with
PWM
= T
PWM Period
Edge-Aligned PWM
CY
Resolution =
• (P
period
X
TPER register at the following instants:
X
TPER + 1) • (P
PWM PERIOD
PWM RESOLUTION
can
log (2 • T
X
TPER buffer contents are
be
log (2)
X
TMR Prescale Value)
PWM
X
determined
TPER is a double-
DS70265B-page 147
/T
CY
)
using