DSPIC33FJ12MC201-I/SO Microchip Technology, DSPIC33FJ12MC201-I/SO Datasheet - Page 169

• Manufacturer Part Number: DSPIC33FJ12MC201-I/SO
• Description: IC DSPIC MCU/DSP 12K 20SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ12MC201-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 12KB (12K x 8)
• Package / Case: 20-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 15
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 15
• Data Ram Size: 1 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.4
The digital noise filter section of the module is
responsible for rejecting noise on the incoming
capture or quadrature signals. Schmitt Trigger inputs
and a 3-clock cycle delay filter combine to reject low-
level noise and large, short-duration noise spikes
that typically occur in noise prone applications, such
as a motor system.
The filter ensures that the filtered output signal is not
permitted to change until a stable value has been
registered for three consecutive clock cycles.
For the QEA, QEB and INDX pins, the clock divide
frequency for the digital filter is programmed by bits
QECK<2:0> (DFLTCON<6:4>), and are derived from
the base instruction cycle, T
To enable the filter output for channels QEA, QEB and
INDX, the QEOUT bit must be ‘1’. The filter network for
all channels is disabled on POR.
15.5
When the QEI module is not configured for the QEI
mode, QEIM<2:0> = 001, the module can be con-
figured as a simple 16-bit timer/counter. The setup and
control of the auxiliary timer is accomplished through
the QEICON SFR register. This timer functions identi-
cally to Timer1. The QEA pin is used as the timer clock
input.
When configured as a timer, the POSCNT register
serves as the Timer Count register, and the MAXCNT
register serves as the Period register. When a Timer/
Period register match occurs, the QEI interrupt flag is
asserted.
The only difference between the general purpose
timers and this timer is the external up/down input
select. When the UPDN pin is asserted high, the timer
increments up. When the UPDN pin is asserted low, the
timer is decremented.
© 2007 Microchip Technology Inc.
Note:
Programmable Digital Noise
Filters
Alternate 16-bit Timer/Counter
Changing the operational mode (for exam-
ple, from QEI to timer or vice versa) will not
affect the Timer/Position Count register
contents.
CY
.
Preliminary
dsPIC33FJ12MC201/202
The UPDN control/status bit (QEICON<11>) can be
used to select the count direction state of the Timer
register. When UPDN = 1, the timer counts up. When
UPDN = 0, the timer counts down.
In addition, control bit UPDN_SRC, (in QEICON<0>),
determines whether the timer count direction state is
based on the logic state written into the UPDN control/
status bit (QEICON<11>) or the QEB pin state:
• When UPDN_SRC = 1, the timer count direction
• When UPDN_SRC = 0, the timer count direction
15.6
During CPU Sleep mode, the following are true for the
QEI module:
• The QEI module is halted.
• The timer does not operate because the internal
15.7
Since the QEI module can function as a Quadrature
Encoder Interface, or as a 16-bit timer, this section
describes operation of the module in both modes.
15.7.1
When the CPU is placed in Idle mode, the QEI module
will operate if QEISIDL (QEICON<13>) = 0. This bit
defaults to a logic ‘0’ upon executing POR. To halt the
QEI module during CPU Idle mode, QEISIDL should
be set to ‘1’.
is controlled from the QEB pin.
is controlled by the UPDN bit.
Note:
clocks are disabled.
QEI Module Operation During CPU
Sleep Mode
QEI Module Operation During CPU
Idle Mode
This alternate timer does not support the
External Asynchronous Counter mode of
operation. If the program uses an external
clock source, the clock will automatically
be synchronized to the internal instruction
cycle.
QEI OPERATION DURING CPU
IDLE MODE
DS70265B-page 167