DSPIC33FJ12MC201-I/SO Microchip Technology, DSPIC33FJ12MC201-I/SO Datasheet - Page 183

• Manufacturer Part Number: DSPIC33FJ12MC201-I/SO
• Description: IC DSPIC MCU/DSP 12K 20SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ12MC201-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 12KB (12K x 8)
• Package / Case: 20-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 15
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 15
• Data Ram Size: 1 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.0
The Inter-Integrated Circuit (I
complete hardware support for both Slave and Multi-
Master modes of the I
standard, with a 16-bit interface.
The I
• The SCLx pin is clock.
• The SDAx pin is data.
The I
• I
• I
• I
• I
• Serial clock synchronization for I
• I
17.1
The hardware fully implements all the master and slave
functions of the I
specifications, as well as 7 and 10-bit addressing.
The I
master on an I
The following types of I
• I
• I
• I
For details about the communication sequence in each
of these modes, refer to the “dsPIC33F Family
Reference Manual” . Please see the Microchip web site
(www.microchip.com) for the latest dsPIC33F Family
Reference Manual chapters.
© 2007 Microchip Technology Inc.
Note:
modes of operation.
master and slaves.
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
collision and arbitrates accordingly.
2
2
2
2
2
2
2
2
C interface supporting both Master and Slave
C Slave mode supports 7 and 10-bit address.
C Master mode supports 7 and 10-bit address.
C port allows bidirectional transfers between
C supports multi-master operation, detects bus
C slave operation with 7-bit address
C slave operation with 10-bit address
C master operation with 7- or 10-bit address
2
2
2
C module has a 2-pin interface:
C module offers the following key features:
C module can operate either as a slave or a
INTER-INTEGRATED CIRCUIT
(I
Operating Modes
2
This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 devices.
It is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
“dsPIC33F Family Reference Manual”.
Please see the Microchip web site
(www.microchip.com)
dsPIC33F
chapters.
C)
2
C bus.
2
C Standard and Fast mode
2
C operation are supported:
Family
2
C serial communication
2
C) module provides
Reference
2
C port can be
for
the
Manual
latest
Preliminary
dsPIC33FJ12MC201/202
17.2
I2CxCON and I2CxSTAT are control and status
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CSTAT are
read/write:
• I2CxRSR is the shift register used for shifting
• I2CxRCV is the receive buffer and the register to
• I2CxTRN is the transmit register to which bytes
• The I2CxADD register holds the slave address.
• A status bit, ADD10, indicates 10-bit Address
• The I2CxBRG acts as the Baud Rate Generator
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV,
and an interrupt pulse is generated.
17.3
The I
• MI2CxIF (I
• SI2CxIF (I
A separate interrupt is generated for all I
conditions.
17.4
In I
Generator (BRG) is located in the I2CxBRG register.
When the BRG is loaded with this value, the BRG
counts down to zero and stops until another reload has
taken place. If clock arbitration is taking place, for
example, the BRG is reloaded when the SCLx pin is
sampled high.
As per the I
400 kHz. However, the user application can specify any
baud rate up to 1 MHz. I2CxBRG values of ‘0’ or ‘1’ are
illegal.
EQUATION 17-1:
data.
which data bytes are written, or from which data
bytes are read.
are written during a transmit operation.
mode.
(BRG) reload value.
2
C Master mode, the reload value for the Baud Rate
2
C module generates two interrupt flags:
I
I
Baud Rate Generator
2
2
I2CxBRG =
C Registers
C Interrupts
2
2
2
C Slave Events Interrupt flag).
C Master Events Interrupt flag)
C standard, F
(
SERIAL CLOCK RATE
F
F
SCL
CY
SCL
–
10,000,000
can be 100 kHz or
F
DS70265B-page 181
CY
2
C error
)
– 1