DSPIC33FJ12MC201-I/SO Microchip Technology, DSPIC33FJ12MC201-I/SO Datasheet - Page 41

• Manufacturer Part Number: DSPIC33FJ12MC201-I/SO
• Description: IC DSPIC MCU/DSP 12K 20SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ12MC201-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 12KB (12K x 8)
• Package / Case: 20-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 15
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 15
• Data Ram Size: 1 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 3-23:
TABLE 3-24:
TABLE 3-25:
File Name
RCON
OSCCON
CLKDIV
PLLFBD
OSCTUN
Legend:
Note
NVMCON
NVMKEY
Legend:
Note
PMD1
PMD2
PMD3
Legend:
File Name
File Name
1:
2:
1:
Addr
0742
0744
0746
0748
0740
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
RCON register Reset values dependent on type of Reset.
OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
Addr
0760
0766
0770
0772
0774
SYSTEM CONTROL REGISTER MAP
NVM REGISTER MAP
PMD REGISTER MAP
TRAPR
Bit 15
IC8MD
ROI
Bit 15
Bit 15
—
—
—
WR
—
—
—
IOPUWR
Bit 14
IC7MD
Bit 14
WREN
Bit 14
—
—
—
—
—
COSC<2:0>
DOZE<2:0>
Bit 13
Bit 13
T3MD
WRERR
—
—
—
Bit 13
—
—
—
Bit 12
Bit 12
T2MD
—
—
—
—
—
Bit 12
—
—
DOZEN
T1MD
Bit 11
Bit 11
—
—
—
—
—
—
Bit 11
—
—
QEIMD
Bit 10
Bit 10
—
—
—
—
—
Bit 10
—
—
FRCDIV<2:0>
NOSC<2:0>
PWM1MD
IC2MD
Bit 9
Bit 9
CM
—
—
—
Bit 9
—
—
VREGS
Bit 8
IC1MD
Bit 8
—
—
—
Bit 8
—
—
CLKLOCK IOLOCK
I2C1MD
EXTR
Bit 7
PLLPOST<1:0>
Bit 7
—
—
—
Bit 7
—
Bit 6
SWR
—
Bit 6
ERASE
—
—
—
Bit 6
SWDTEN
LOCK
Bit 5
U1MD
—
Bit 5
—
—
Bit 5
—
PLLDIV<8:0>
WDTO
PWM2MD
Bit 4
—
Bit 4
Bit 4
—
—
NVMKEY<7:0>
—
SLEEP
Bit 3
SPI1MD
CF
Bit 3
Bit 3
—
—
TUN<5:0>
PLLPRE<4:0>
Bit 2
IDLE
—
Bit 2
Bit 2
—
—
—
NVMOP<3:0>
LPOSCEN
Bit 1
BOR
OC2MD
Bit 1
Bit 1
—
—
OSWEN
AD1MD
OC1MD
Bit 0
POR
Bit 0
Bit 0
—
Resets
xxxx
0300
0040
0030
0000
Resets
Resets
0000
0000
0000
0000
0000
All
All
All
(1)
(2)
(1)