DSPIC33FJ12MC201-I/SO Microchip Technology, DSPIC33FJ12MC201-I/SO Datasheet - Page 280

IC DSPIC MCU/DSP 12K 20SOIC

DSPIC33FJ12MC201-I/SO

Manufacturer Part Number
DSPIC33FJ12MC201-I/SO
Description
IC DSPIC MCU/DSP 12K 20SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ12MC201-I/SO

Program Memory Type
FLASH
Program Memory Size
12KB (12K x 8)
Package / Case
20-SOIC (7.5mm Width)
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
15
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
15
Data Ram Size
1 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
dsPIC33FJ12MC201/202
Reset
Reset Sequence.................................................................. 61
Resets ................................................................................. 55
S
Serial Peripheral Interface (SPI) ....................................... 173
Setup for Continuous Output Pulse Generation................ 139
Setup for Single Output Pulse Generation ........................ 139
Software Simulator (MPLAB SIM)..................................... 226
Software Stack Pointer, Frame Pointer
Special Features of the CPU............................................. 211
SPI
SPI Module
Symbols Used in Opcode Descriptions............................. 218
System Control
T
Temperature and Voltage Specifications
Timer1 ............................................................................... 129
Timer2/3 ............................................................................ 131
Timing Characteristics
Timing Diagrams
DS70265B-page 278
T2CON Control ......................................................... 134
T3CON Control ......................................................... 135
TCxCON (Input Capture x Control) ........................... 138
UxMODE (UARTx Mode) .......................................... 194
UxSTA (UARTx Status and Control) ......................... 196
Clock Source Selection ............................................... 58
Special Function Register Reset States ..................... 59
Times .......................................................................... 58
CALLL Stack Frame.................................................... 40
Master, Frame Master Connection ........................... 175
Master/Slave Connection .......................................... 175
Slave, Frame Master Connection ............................. 176
Slave, Frame Slave Connection ............................... 176
SPI1 Register Map ...................................................... 34
Register Map............................................................... 39
AC ............................................................................. 238
CLKO and I/O ........................................................... 241
10-bit A/D Conversion (CHPS = 01, SIMSAM = 0,
10-bit A/D Conversion (CHPS = 01, SIMSAM = 0,
12-bit A/D Conversion (ASAM = 0, SSRC = 000) ..... 264
Center-Aligned PWM ................................................ 148
Dead-Time ................................................................ 150
Edge-Aligned PWM................................................... 148
External Clock ........................................................... 239
I2Cx Bus Data (Master Mode) .................................. 257
I2Cx Bus Data (Slave Mode) .................................... 259
I2Cx Bus Start/Stop Bits (Master Mode) ................... 257
I2Cx Bus Start/Stop Bits (Slave Mode) ..................... 259
Input Capture (CAPx)................................................ 247
Motor Control PWM .................................................. 249
Motor Control PWM Fault ......................................... 249
OC/PWM ................................................................... 248
Output Compare (OCx) ............................................. 247
QEA/QEB Input ......................................................... 250
QEI Module Index Pulse ........................................... 251
Reset, Watchdog Timer, Oscillator Start-up
SPIx Master Mode (CKE = 0).................................... 252
SPIx Master Mode (CKE = 1).................................... 253
SPIx Slave Mode (CKE = 0)...................................... 254
SPIx Slave Mode (CKE = 1)...................................... 255
Timer1, 2 and 3 External Clock................................. 244
ASAM = 0, SSRC = 000) .................................. 265
ASAM = 1, SSRC = 111, SAMC = 00001)........ 265
Timer and Power-up Timer ............................... 242
Preliminary
Timing Requirements
Timing Specifications
U
UART
UART Module
Universal Asynchronous Receiver Transmitter (UART) ... 191
V
Voltage Regulator (On-Chip) ............................................ 214
W
Watchdog Timer (WDT)............................................ 211, 215
WWW Address ................................................................. 279
WWW, On-Line Support ....................................................... 6
TimerQ (QEI Module) External Clock ....................... 246
CLKO and I/O ........................................................... 241
External Clock........................................................... 239
Input Capture ............................................................ 247
10-bit A/D Conversion Requirements ....................... 266
12-bit A/D Conversion Requirements ....................... 264
I2Cx Bus Data Requirements (Master Mode)........... 258
I2Cx Bus Data Requirements (Slave Mode)............. 260
Motor Control PWM Requirements........................... 249
Output Compare Requirements................................ 247
PLL Clock ................................................................. 240
QEI External Clock Requirements ............................ 246
QEI Index Pulse Requirements ................................ 251
Quadrature Decoder Requirements.......................... 250
Reset, Watchdog Timer, Oscillator Start-up Timer,
Simple OC/PWM Mode Requirements ..................... 248
SPIx Master Mode (CKE = 0) Requirements............ 252
SPIx Master Mode (CKE = 1) Requirements............ 253
SPIx Slave Mode (CKE = 0) Requirements.............. 254
SPIx Slave Mode (CKE = 1) Requirements.............. 256
Timer1 External Clock Requirements ....................... 244
Timer2 External Clock Requirements ....................... 245
Timer3 External Clock Requirements ....................... 245
Baud Rate
Break and Sync Transmit Sequence ........................ 193
Flow Control Using UxCTS and UxRTS Pins ........... 193
Receiving in 8-bit or 9-bit Data Mode ....................... 193
Transmitting in 8-bit Data Mode................................ 193
Transmitting in 9-bit Data Mode................................ 193
UART1 Register Map.................................................. 34
Programming Considerations ................................... 215
Power-up Timer and Brown-out Reset
Requirements ................................................... 243
Generator (BRG) .............................................. 192
© 2007 Microchip Technology Inc.

Related parts for DSPIC33FJ12MC201-I/SO