DSPIC33FJ12MC201-I/SO Microchip Technology, DSPIC33FJ12MC201-I/SO Datasheet - Page 168

• Manufacturer Part Number: DSPIC33FJ12MC201-I/SO
• Description: IC DSPIC MCU/DSP 12K 20SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ12MC201-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 12KB (12K x 8)
• Package / Case: 20-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 15
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 15
• Data Ram Size: 1 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33FJ12MC201/202
15.1
A typical incremental (or optical) encoder has three
outputs: Phase A, Phase B and an index pulse. These
signals are useful and often required in position and
speed control of ACIM and SR motors.
The two channels, Phase A (QEA) and Phase B (QEB),
have a unique relationship. If Phase A leads Phase B,
the direction of the motor is deemed positive or for-
ward. If Phase A lags Phase B, the direction of the
motor is deemed negative or reverse.
A third channel, termed index pulse, occurs once per
revolution and is used as a reference to establish an
absolute position. The index pulse coincides with
Phase A and Phase B, both low.
15.2
The 16-bit up/down counter counts up or down on
every count pulse, which is generated by the difference
of the Phase A and Phase B input signals. The counter
acts as an integrator whose count value is proportional
to position. The direction of the count is determined by
the UPDN signal, which is generated by the
Quadrature Encoder Interface logic.
15.2.1
Position counter error checking in the QEI is provided
for and indicated by the CNTERR bit (QEICON<15>).
The error checking applies only when the position
counter is configured for Reset on the Index Pulse
modes (QEIM<2:0> = 110 or 100). In these modes, the
contents of the POSCNT register are compared with
the values (0xFFFF or MAXCNT + 1, depending on
direction).
If these values are detected, the CNTERR bit is set,
generating an error condition, and a QEI counter error
interrupt is generated. The QEI counter error interrupt
can
(DFLTCON<8>).
The position counter continues to count encoder edges
after an error has been detected. The POSCNT regis-
ter continues to count up/down until a natural rollover/
underflow. No interrupt is generated for the natural
rollover/underflow event.
The CNTERR bit is a read/write bit and is reset in
software by the user application.
15.2.2
The Position Counter Reset Enable bit, POSRES
(QEI<2>), controls whether the position counter is reset
when the index pulse is detected. This bit is applicable
only when QEIM<2:0> = 100 or 110.
DS70265B-page 166
be
Quadrature Encoder Interface
Logic
16-bit Up/Down Position
Counter Mode
POSITION COUNTER ERROR
CHECKING
disabled
POSITION COUNTER RESET
by
setting
the
CEID
Preliminary
bit
If the POSRES bit is set to ‘1’, the position counter is
reset when the index pulse is detected. If the POSRES
bit is set to ‘0’, the position counter is not reset when
the index pulse is detected. The position counter con-
tinues counting up or down, and is reset on the rollover
or underflow condition.
The interrupt is still generated on the detection of the
index pulse and not on the position counter overflow/
underflow.
15.2.3
The QEI logic generates a UPDN signal, based upon
the relationship between Phase A and Phase B. In
addition to the output pin, the state of this internal
UPDN signal is supplied to an SFR bit, UPDN
(QEICON<11>), as a read-only bit. To place the state of
this signal on an I/O pin, the SFR bit, PCDOUT
(QEICON<6>), must be set to ‘1’.
15.3
Two measurement modes are supported, x2 and x4.
These modes are selected by the QEIM<2:0> mode
select bits located in SFR QEICON<10:8>.
When control bits QEIM<2:0> = 100 or 101, the x2
Measurement mode is selected and the QEI logic only
looks at the Phase A input for the position counter
increment rate. Every rising and falling edge of the
Phase A signal causes the position counter to be
incremented or decremented. The Phase B signal is
still used for the determination of the counter direction.
Within the x2 Measurement mode, there are two
variations of how the position counter is reset:
• Position counter reset by detection of index pulse,
• Position counter reset by match with MAXCNT,
When control bits QEIM<2:0> = 110 or 111, the x4
Measurement mode is selected and the QEI logic looks
at both edges of the Phase A and Phase B input
signals. Every edge of both signals causes the position
counter to increment or decrement.
Within the x4 Measurement mode, the position counter
can be reset two ways:
• Position counter reset by detection of index pulse,
• Position counter reset by match with MAXCNT,
The x4 Measurement mode provides for finer
resolution data (more position counts) for determining
motor position.
QEIM<2:0> = 100
QEIM<2:0> = 101
QEIM<2:0> = 110.
QEIM<2:0> = 111.
Position Measurement Mode
COUNT DIRECTION STATUS
© 2007 Microchip Technology Inc.