ST72F521M9T6 STMicroelectronics, ST72F521M9T6 Datasheet - Page 134

• Manufacturer Part Number: ST72F521M9T6
• Description: IC MCU 8BIT 60K FLASH 80-TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F521M9T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Processor Series: ST72F5x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 2048 B
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 3.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• For Use With: 497-6453 - BOARD EVAL BASED ON ST7LNBX497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-8244; ST72F521M9T6

ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
– ERROR. The error management as described in
Figure 71. CAN Error State Diagram
134/215
the CAN protocol is completely handled by hard-
ware using 2 error counters which get increment-
ed or decremented according to the error
condition. Both of them may be read by the appli-
When 128 * 11 recessive bits occur:
- the BOFF bit gets cleared
- the TECR register gets cleared
- the RECR register gets cleared
ERROR ACTIVE
When TECR or RECR > 127, the EPSV bit gets set
the EPSV bit gets cleared
When TECR and RECR < 128,
BUS OFF
cation to determine the stability of the network.
Moreover, as one of the node status bits (EPSV
or BOFF of the CSR register) changes, an inter-
rupt is generated if the SCIE bit is set in the ICR
Register. Refer to
ERROR PASSIVE
When TECR > 255 the BOFF bit gets set
and the EPSV bit gets cleared
Figure
71.