ST72F521M9T6 STMicroelectronics, ST72F521M9T6 Datasheet - Page 152

• Manufacturer Part Number: ST72F521M9T6
• Description: IC MCU 8BIT 60K FLASH 80-TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F521M9T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Processor Series: ST72F5x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 2048 B
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 3.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• For Use With: 497-6453 - BOARD EVAL BASED ON ST7LNBX497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-8244; ST72F521M9T6

ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
The worst case is when the abort request is done
when the transmission has just started. In this
case the LOCK bit cannot be reset as long as the
BUSY bit is set, this means until the end of the
frame. So the application will wait for READY to be
reset during the whole frame and in this case the
worst case will be the longest frame the applica-
tion is expected to transmit.
Figure 81. Abort with the software work-around
- by NRTX, BUSY and LOCK
Using the software work-around the worst case
occurs in the arbitration lost case. If the abort is re-
quested just after pCAN has lost the arbitration
then the application has to wait for the next falling
edge of the BUSY bit before the LOCK bit can be
152/215
TX RQST
ABORT RQST
CAN TX
CAN RX
LOCK
READY
BUSY
NRTX
reset. If the next arbitration is won by pCAN then
the BUSY bit will be reset by the end of the suc-
cessful transmission. The longest time the applica-
tion has to wait in this case is the time of the long-
est message expected on the bus (minus identifi-
er) plus the longest message expected to be trans-
mitted by the application. This roughly double the
time the application may have to wait before the
abort sequence is performed.
10.8.5.4 WKPS Functionality
Due to a fix implemented to solve the “Unexpected
Message Transmission” issue (see
10.8.5.3) the WKPS functionality has been modi-
fied as follows in Flash ST72F521 devices:
Flash
ST72F521
Rev R
ROM
ST72521 All
revisions
Device
WKPS bit does not generate a wakeup
pulse. It is used to synchronize the re-
set of the LOCK bit (see
Work-around - Devices with Hardware
Fix (ST72F521 rev “R”):” on page
WKPS bit functions according to the
datasheet description.
Modification
“Software
Section
148)