ST72F521M9T6 STMicroelectronics, ST72F521M9T6 Datasheet - Page 149

IC MCU 8BIT 60K FLASH 80-TQFP

ST72F521M9T6

Manufacturer Part Number
ST72F521M9T6
Description
IC MCU 8BIT 60K FLASH 80-TQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST72F521M9T6

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LINSCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Processor Series
ST72F5x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
2048 B
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
64
Number Of Timers
5
Operating Supply Voltage
3.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
For Use With
497-6453 - BOARD EVAL BASED ON ST7LNBX497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
497-8244
ST72F521M9T6

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CONTROLLER AREA NETWORK (Cont’d)
Software Work-around - Devices without Hard-
ware Fix:
To implement a transmission abort under safe
conditions, any reset of the LOCK bit during the
critical window (2 bit times) must be avoided. Two
different cases have to be considered, either the
pCAN enters standby mode after the abort, or the
abort is performed and pCAN keeps running.
Abort followed by STANDBY mode (RUN=0)
In this case, aborting the pending transmissions
can safely be done by first entering STANDBY
mode and then releasing the transmit buffers.
STANDBY mode is entered by resetting the RUN
bit in the CSR register and once the current trans-
mission attempt, even if it fails due to error or lost
arbitration, has been performed, pCAN enters
STANDBY mode (RUN=0). Once in STANDBY
mode the application can abort all pending trans-
missions by resetting the corresponding LOCK bit.
_asm("SIM\n");
CANCSR |= NRTX;
while(!(CANBCSR & BUSY) &&// Wait till BUSY bit is set
while( CANBCSR & BUSY ); // Wait till BUSY bit is reset (falling edge)
if( CANBCSR & RDY )
{ // transmission still pending -> must be aborted
}
else
{ // No more abort required as RDY bit already reset
}
CANBCSR &= ~LOCK; //Arbitration lost => cancel transmission safel
while( CANBCSR & RDY );// Wait for unlock confirmed
CANCSR &= ~NRTX;// Reset NRTX bit once abort sequence done
_asm("RIM\n");
CANCSR &= ~NRTX;// Reset NRTX bit once abort sequence done
_asm("RIM\n"); // Enable interrupts
(CANBCSR & RDY) ); // or transmission done
// Mask interrupts
// Set non automatic retransmission bit
Abort while staying in RUN mode (RUN=1)
Contrary to the STANDBY case described previ-
ously, in the RUN case the application has to han-
dle the error or arbitration lost conditions. In case
of transmission errors, causing the frame to be
transmitted again and again, the application must
set the NRTX bit in the CSR register. This will
cause pCAN to abort the transmission at the end
of the current attempt.
In case of arbitration lost, setting the NRTX bit
does not abort the transmission, therefore the ap-
plication must reset the LOCK bit to abort the
transmission. To avoid resetting the LOCK bit dur-
ing the critical time window, leading to the problem
described at the start of this section, the applica-
tion must monitor the BUSY bit in the BCSR regis-
ter and reset the LOCK bit just after the falling
edge of the BUSY bit. The time between the falling
edge of the BUSY bit and the SOF of the next
transmission attempt is in any case long enough to
guarantee that the LOCK bit is reset before the
critical time window.
The “C” code sequence below shows the software
work-around for both the error and arbitration lost
cases.
ST72F521, ST72521B
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