ST72F521M9T6 STMicroelectronics, ST72F521M9T6 Datasheet - Page 146

• Manufacturer Part Number: ST72F521M9T6
• Description: IC MCU 8BIT 60K FLASH 80-TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F521M9T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Processor Series: ST72F5x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 2048 B
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 3.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• For Use With: 497-6453 - BOARD EVAL BASED ON ST7LNBX497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-8244; ST72F521M9T6

ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
10.8.5 List of CAN Cell Limitations
10.8.5.1 Omitted SOF bit
Symptom:
Start of Frame (SOF) bit is omitted if transmission
is requested in the last Intermission bit.
Test Case:
5.3.1 10-Kbit Stress Test
Details:
The IUT is requested to start transmission immedi-
ately after the completion of the previous transmis-
sion. The LT also starts its transmission and as-
serts the SOF bit just after the 3
The IUT also starts transmission but omits the
SOF bit. The IUT wins the arbitration and contin-
ues the transmission. The frame is sent correctly.
Impact On The Application:
As this effect only occurs when the IUT detects a
SOF bit on the CAN bus, the fact that it omits its
own SOF bit has no impact on the communication.
10.8.5.2 CAN: CPU Write Access (More Than
One Cycle) Corrupts CAN Frame
Symptoms:
For CAN received messages the identifier high
byte or last data byte can be corrupted.
146/215
rd
Intermission bit.
For CAN transmitted messages the 2nd data byte
can be corrupted.
Details:
The CAN transmit and receive buffers are imple-
mented as dual ported RAM. During the reception
of a CAN frame the CAN core writes the received
identifier and the data byte-by-byte in the corre-
sponding buffer.
IF the CAN bit timing configuration is t
quanta
AND
IF concurrently with the pCAN, the CPU executes
a write access to the dual ported RAM using an in-
struction with more than one cycle access, e.g.
CLR, BSET, BRES
THEN the access conflict can lead to the corrup-
tion described in the symptoms paragraph above.
Impact On The Application:
Several CAN frames with erroneous data or iden-
tifier will be received/transmitted.
Software Workaround:
Program t
the receive or transmit buffers, do not use the crit-
ical instructions which are:
BSET, BRES, CLR, CPL, DEC, INC, NEG, RLC,
SLL, SRL, RRC, SRA, SWAP.
BS2
> 4 time quanta or, when accessing
BS2
< 5 time