ST72F521M9T6 STMicroelectronics, ST72F521M9T6 Datasheet - Page 138

IC MCU 8BIT 60K FLASH 80-TQFP

ST72F521M9T6

Manufacturer Part Number
ST72F521M9T6
Description
IC MCU 8BIT 60K FLASH 80-TQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST72F521M9T6

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LINSCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Processor Series
ST72F5x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
2048 B
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
64
Number Of Timers
5
Operating Supply Voltage
3.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
For Use With
497-6453 - BOARD EVAL BASED ON ST7LNBX497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
497-8244
ST72F521M9T6

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ST72F521, ST72521B
CONTROLLER AREA NETWORK (Cont’d)
CONTROL/STATUS REGISTER (CSR)
Read/Write
Reset Value: 00h
Bit 6 = BOFF Bus-Off State
Set by hardware to indicate that the node is in bus-
off state, i.e. the Transmit Error Counter exceeds
255.
Reset by hardware to indicate that the node is in-
volved in bus activities.
Bit 5 = EPSV Error Passive State
Set by hardware to indicate that the node is error
passive.
Reset by hardware to indicate that the node is either
error active (BOFF = 0) or bus-off.
Bit 4 = SRTE Simultaneous Receive/Transmit En-
able
Set by software to enable simultaneous transmis-
sion and reception of a message passing the ac-
ceptance filtering. Allows to check the integrity of
the communication path.
Reset by software to discard all messages trans-
mitted by the node. Allows remote and data frames
to share the same identifier.
138/215
Read Only
Read Only
7
0
BOFF EPSV SRTE NRTX FSYN WKPS
Read/Set/Clear
RUN
0
Bit 3 = NRTX No Retransmission
Set by software to disable the retransmission of un-
successful messages. It does not stop transmission
in case of Arbitration Lost.
Cleared by software to enable retransmission of
messages until success is met.
Bit 2 = FSYN Fast Synchronization
Set by software to enable a fast resynchronization
when leaving standby mode, i.e. wait for only 11 re-
cessive bits in a row.
Cleared by software to enable the standard resyn-
chronization when leaving standby mode, i.e. wait
for 128 sequences of 11 recessive bits.
Bit 1 = WKPS Wake-up Pulse
Set by software to generate a dominant pulse when
leaving standby mode.
Cleared by software for no dominant wake-up
pulse.
Bit 0 = RUN CAN Enable
Set by software to leave standby mode after 128 se-
quences of 11 recessive bits or just 11 recessive
bits if FSYN is set.
Cleared by software to request a switch to the
standby or low-power mode as soon as any on-go-
ing transfer is complete. Read-back as 1 in the
meantime to enable proper signalling of the standby
state. The CPU clock may therefore be safely
switched OFF whenever RUN is read as 0.
Read/Set/Clear
Read/Set/Clear
Read/Set/Clear
Read/Set/Clear

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