ST72F521M9T6 STMicroelectronics, ST72F521M9T6 Datasheet - Page 153

• Manufacturer Part Number: ST72F521M9T6
• Description: IC MCU 8BIT 60K FLASH 80-TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F521M9T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Processor Series: ST72F5x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 2048 B
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 3.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• For Use With: 497-6453 - BOARD EVAL BASED ON ST7LNBX497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-8244; ST72F521M9T6

CONTROLLER AREA NETWORK (Cont’d)
10.8.5.5 Bus-off state not entered
Symptom:
pCAN does not enter bus-off state under certain
conditions. This is fixed in FLASH version of
ST72F521 starting from silicon Rev R and in ROM
version ST72521B starting from silicon Rev Y.
Details:
According to the CAN standard, pCAN is expected
to enter bus-off state when TEC (Transmit Error
Counter) is greater than 255.
But if REC (Receive Error Counter) is greater than
127 (Error Passive State) pCAN does not enter
bus-off and the BOFF bit of the CSR register is not
set. To enter bus-off, REC must decrease to a val-
Figure 82. CAN Error State Diagram showing “BUSOFF not entered” limitation
When 128 * 11 recessive bits occur:
- the BOFF bit gets cleared
- the TECR register gets cleared
- the RECR register gets cleared
ERROR ACTIVE
When TECR or RECR > 127, the EPSV bit gets set
the EPSV bit gets cleared
When TECR and RECR < 128,
BUS OFF
ue lower than 128, this is the case with any correct
reception even if the message is filtered out.
As bus-off state is not entered and pCAN still at-
tempts to transmit its message, after the overflow
the TEC register continues to increment as long as
transmission errors occur.
Impact on the application:
The application will not stop attempting to transmit
CAN messages, even when the bus-off conditions
have been reached, until the transmission has
been successful or the value of REC becomes
lower than 128. However the application will not
disturb the communication of the other nodes on
the CAN network as pCAN is in Error Passive
State.
ERROR PASSIVE
When TECR > 255 and RECR < 128 the BOFF bit
gets set and the EPSV bit gets cleared
ST72F521, ST72521B
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