ST92F150CV1TB STMicroelectronics, ST92F150CV1TB Datasheet - Page 247

• Manufacturer Part Number: ST92F150CV1TB
• Description: MCU 8BIT 128K FLASH 100TQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150CV1TB

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4883

ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CONTROL REGISTER 2 (SCICR2)
R244 - Read/Write
Register Page: 26
Reset Value: 0000 0000 (00h)
Bit 7 = TIE Transmitter interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever
Bit 6 = TCIE Transmission complete interrupt ena-
ble
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC=1 in
Bit 5 = RIE Receiver interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR=1
Bit 4 = ILIE Idle line interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE=1
Bit 3 = TE Transmitter enable.
This bit enables the transmitter. It is set and
cleared by software.
0: Transmitter is disabled, the TDO pin is in high
1: Transmitter is enabled
Note: during transmission, a “0” pulse on the TE
bit (“0” followed by “1”) sends a preamble after the
current word.
Bit 2 = RE Receiver enable.
This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled, it resets the RDRF, IDLE,
1: Receiver is enabled and begins searching for a
TIE
TDRE=1 in the SCISR register
the SCISR register
or RDRF=1 in the SCISR register
in the SCISR register.
impedance
OR, NF and FE bits of the SCISR register
start bit
7
TCIE
RIE
ILIE
ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A)
TE
RE
RWU
SBK
0
Bit 1 = RWU Receiver wake-up.
This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
0: Receiver in active mode
1: Receiver in mute mode
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Notes:
– If the SBK bit is set to “1” and then to “0”, the
– The ITEI0 bit in the SITRH register (See Inter-
CONTROL REGISTER 3 (SCICR3)
R255 - Read/Write
Register Page: 26
Reset Value: 0000 0000 (00h)
Bit 7 = Reserved
Bit 6 = LINE LIN mode Enable.
This bit is set and cleared by software.
0: LIN master mode disabled
1: LIN master mode enabled
LIN master mode enables the capability to send
LIN Synch Breaks (13 low bits) using the SBK bit
in the SCICR2 register. In transmission, the LIN
Synch Break low phase duration is shown as be-
low:
Bits 5:0 = Reserved
transmitter will send a BREAK word at the end of
the current word.
rupts Chapter) must be set to enable the SCI-A
interrupt as the SCI-A interrupt is a rising edge
event.
7
-
LINE
0
0
1
1
LINE
M
0
1
0
1
-
-
during a LIN Synch Break
Number of low bits sent
-
10
11
13
14
-
-
247/429
0
-
9