ST92F150CV1TB STMicroelectronics, ST92F150CV1TB Datasheet - Page 57

• Manufacturer Part Number: ST92F150CV1TB
• Description: MCU 8BIT 128K FLASH 100TQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150CV1TB

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4883

REGISTER DESCRIPTION (Cont’d)
When in Erase Suspend the memory accepts only
the following operations: Read, Erase Resume
and Byte Program. Updating the
not possible during a Flash Erase Suspend.
0: Resume sector erase when FWMS is set again.
1: Suspend Sector erase
Bit 1 = PROT: Set Protection (Read/Write).
This bit must be set to select the Set Protection op-
eration. This bit is automatically reset at the end of
the Set Protection operation.
The Set Protection operation allows “0”s in place
of “1”s to be programmed in the four Non Volatile
Protection registers. From 1 to 4 bytes can be en-
tered (in any order, no need for an ordered ad-
dress sequence) before starting the execution by
setting the FWMS bit. Data to be programmed and
addresses in which to program must be provided
(through an LD instruction, for example). Protec-
tion contained in addresses that are not entered
are left unchanged.
0: Deselect protection
1: Select protection
Bit 0 = FBUSY: Flash Busy (Read Only).
This bit is automatically set during Page Program,
Byte Program, Sector Erase or Set Protection op-
erations when the first address to be modified is
latched in Flash memory, or during Chip Erase op-
eration when bit FWMS is set. When this bit is set
every read access to the Flash memory will output
invalid data (FFh equivalent to a NOP instruction),
while every write access to the Flash memory will
be ignored. At the end of the write operations or
during a Sector Erase Suspend this bit is automat-
ically reset and the memory returns to read mode.
After an Erase Resume this bit is automatically set
again. The FBUSY bit remains high for a maxi-
mum of 10μs after Power-Up and when exiting
Power-Down mode, meaning that the Flash mem-
ory is not yet ready to be accessed.
0: Flash not busy
1: Flash busy
ST92F124/F150/F250 - SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)
E
3 TM
memory is
E
Address: 224001h /221001h- Read/Write
Reset value: 000x x000 (xxh)
The
operations for the
The ECR also contains two bits (WFIS and FEIEN)
that are related to both Flash and
Bit 7 = EWMS:
This bit must be set to start every write/erase oper-
ation in the
erase operation this bit is automatically reset. Re-
setting by software this bit does not stop the cur-
rent write operation.
0: No effect
1: Start
Bit 6 = EPAGE:
This bit must be set to select the Page Update op-
eration in
tion allows to write a new content: both “0”s in
place of “1”s and “1”s in place of “0”s. From 1 to 16
bytes can be entered (in any order, no need for an
ordered address sequence) before starting the ex-
ecution by setting bit EWMS. All the addresses
must belong to the same page (only the 4 LSBs of
address can change). Data to be programmed and
addresses in which to program must be provided
(through an LD instruction, for example). Data
contained in page addresses that are not entered
are left unchanged. This bit is automatically reset
at the end of the Page Update operation.
0: Deselect page update
1: Select page update
Bit 5 = ECHIP:
This bit must be set to select the Chip Erase oper-
ation in the
tion allows to erase all the
The execution starts by setting bit EWMS. This bit
is automatically reset at the end of the Chip Erase
operation.
0: Deselect chip erase
1: Select chip erase
Bit 4:3 = Reserved.
EWMS EPAGE ECHIP
3 TM
7
E
CONTROL REGISTER (ECR)
3 TM
E
3 TM
6
Control Register is used to enable all the
E
3 TM
E
E
3 TM
3 TM
write
E
E
memory. The Page Update opera-
5
E
3 TM
3 TM
memory. The Chip Erase opera-
memory. At the end of the write/
3 TM
E
3 TM
chip erase.
Write Mode Start.
4
page update.
memory.
3
E
3 TM
WFIS FEIEN EBUSY
locations to FFh.
2
E
3 TM
memories.
1
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