HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 258

• Manufacturer Part Number: HD64F3664FPV
• Description: IC H8/3664 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664FPV

• Core Size: 16-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: External
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• No. Of I/o's: 29
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev. 5.00, 03/04, page 230 of 388
Bit Bit Name
6
5
4
3
2
IEIC
MST
TRS
ACKE
BBSY
Initial Value R/W
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
I
When this bit is 1, Interrupts are enabled by IRIC.
Master/Slave Select
Transmit/Receive Select
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Both these bits will be cleared by hardware when they lose
in a bus contention in master mode of the I
slave receive mode, the R/W bit in the first frame
immediately after the start automatically sets these bits in
receive mode or transmit mode by using hardware. The
settings can be made again for the bits that were
set/cleared by hardware, by reading these bits. When the
TRS bit is intended to change during a transfer, the bit will
not be switched until the frame transfer is completed,
including acknowledgement.
Acknowledge Bit Judgement Selection
0: The value of the acknowledge bit is ignored, and
1: If the acknowledge bit is 1, continuous transfer is
Bus Busy
In slave mode, reading the BBSY flag enables to confirm
whether the I
is set to 0 when the SDA level changes from high to low
under the condition of SCl = high, assuming that the start
condition has been issued. The BBSY flag is cleared to 0
when the SDA level changes from low to high under the
condition of SCl = high, assuming that the start condition
has been issued. Writing to the BBSY flag in slave mode is
disabled.
In master mode, the BBSY flag is used to issue start and
stop conditions. Write 1 to BBSY and 0 to SCP to issue a
start condition. Follow this procedure when also re-
transmitting a start condition. To issue a start/stop
condition, use the MOV instruction. The I
must be set in master transmit mode before the issue of a
start condition.
2
C Bus Interface Interrupt Enable
continuous transfer is performed. The value of the
received acknowledge bit is not indicated by the ACKB
bit, which is always 0.
interrupted.
2
C bus is occupied or released. The BBSY flag
2
C bus interface
2
C bus format. In