HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 272

• Manufacturer Part Number: HD64F3664FPV
• Description: IC H8/3664 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664FPV

• Core Size: 16-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: External
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• No. Of I/o's: 29
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4. When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of
5. To continue transmission, clear the IRIC flag to 0, then write the next data to be transmitted
Transmit operations can be performed continuously by repeating steps [4] and [5]. To end
transmission, write H'FF to ICDR. When SDA is changed from low to high when SCL is high,
and the stop condition is detected, the BBSY flag in ICCR is cleared to 0.
Rev. 5.00, 03/04, page 244 of 388
(master output)
(master output)
(slave output)
User processing
(slave output)
slave device sequentially sends the data written into ICDR in accordance with the clock output
by the master device at the timing shown in figure 15.9.
the 9th transmit clock pulse. If the TDRE internal flag has been set to 1, this slave device
drives SCL low from the fall of the transmit clock until data is written to ICDR. The master
device drives SDA low at the 9th clock pulse, and returns an acknowledge signal. As this
acknowledge signal is stored in the ACKB bit in ICSR, this bit can be used to determine
whether the transfer operation was performed normally. When the TDRE internal flag is 0, the
data written into ICDR is transferred to ICDRS, transmission is started, and the TDRE internal
flag and the IRIC and IRTR flags are set to 1 again.
into ICDR. The TDRE flag is cleared to 0.
ICDRS
SDA
ICDRT
TDRE
SCL
SDA
SCL
IRIC
Slave receive mode
Figure 15.9 Example of Slave Transmit Mode Operation Timing
R/W
8
[3] IRIC
clearance
Interrupt
request
generation
A
9
[2]
[3] ICDR
write
Slave transmit mode
Data 1
Bit 7
Interrupt
request
generation
1
Data 1
Bit 6
2
[3] ICDR
write
(MLS = 0)
Bit 5
3
Bit 4
Data 1
Data 2
4
Bit 3
5
Bit 2
6
Bit 1
7
[5] IRIC
clearance
Bit 0
8
9
Interrupt
request
generation
A
[3]
Data 2
Bit 7
1
[5] ICDR
write
Data 2
Bit 6
2