HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 83

• Manufacturer Part Number: HD64F3664FPV
• Description: IC H8/3664 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664FPV

• Core Size: 16-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: External
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• No. Of I/o's: 29
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WKP5 to WKP0 Interrupts
3.4.2
Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to
enable or disable the interrupt. For timer A interrupt requests and direct transfer interrupt requests
generated by execution of a SLEEP instruction, this function is included in IRR1 and IENR1.
When an on-chip peripheral module requests an interrupt, the corresponding interrupt request
status flag is set to 1, requesting the CPU of an interrupt. When this interrupt is accepted, the I bit
is set to 1 in CCR. These interrupts can be masked by writing 0 to clear the corresponding enable
bit.
WKP5 to WKP0 interrupts are requested by input signals to pins WKP5 to WKP0. These six
interrupts have the same vector addresses, and are detected individually by either rising edge
sensing or falling edge sensing, depending on the settings of bits WPEG5 to WPEG0 in
IEGR2.
When pins WKP5 to WKP0 are designated for interrupt input in PMR5 and the designated
signal edge is input, the corresponding bit in IWPR is set to 1, requesting the CPU of an
interrupt. These interrupts can be masked by setting bit IENWP in IENR1.
Internal Interrupts
RES
ø
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus (16 bits)
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) Initial program instruction
Figure 3.1 Reset Sequence
Vector fetch
Reset cleared
(2)
(1)
Internal
processing
Rev. 5.00, 03/04, page 55 of 388
Initial program
instruction prefetch
(2)
(3)