HD64F3664FPV Renesas Electronics America, HD64F3664FPV Datasheet - Page 300

• Manufacturer Part Number: HD64F3664FPV
• Description: IC H8/3664 MCU FLASH 32K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664FPV

• Core Size: 16-Bit
• Program Memory Size: 32KB (32K x 8)
• Oscillator Type: External
• Core Processor: H8/300H
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• No. Of I/o's: 29
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: H8/300H
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.4
17.4.1
This LSI has a multi-chip structure with two internal chips of F-ZTAT™ HD64F3664 and 512-
byte EEPROM.
The EEPROM interface is the I
communication with the external devices connected to the I
17.4.2
The I
specific for the EEPROM are the following two.
1. The EEPROM address is configured of two bytes, the write data is transferred in the order of
2. The write data is transmitted from the MSB side.
The bus format and bus timing of the EEPROM are shown in figure 17.2.
17.4.3
A high-to-low transition of the SDA input with the SCL input high is needed to generate the start
condition for starting read, write operation.
17.4.4
A low-to-high transition of the SDA input with the SCL input high is needed to generate the stop
condition for stopping read, write operation.
Rev. 5.00, 03/04, page 272 of 388
SDA
SCL
Legend: R/W: R/W code (0 is for a write and 1 is for a read),
upper address and lower address from each MSB side.
condition
Start
2
C bus format and the I
ACK: acknowledge
Operation
EEPROM Interface
Bus Format and Timing
Start Condition
Stop Condition
1
2
Slave address
3
4
Figure 17.2 EEPROM Bus Format and Bus Timing
5
6
2
C bus timing follow section 15.4.1, I
7
2
C bus interface. This I
R/W ACK
8
9
Upper memory
A15
1
address
A8
8
ACK
9
A7
lower memory
1
2
C bus is open to the outside, so the
address
2
C bus can be made.
A0
8
ACK
9
2
C Bus Format. The bus formats
D7
1
Data
D0
8
ACK
9
D7
1
Data
D0
8
ACK
9
conditon
Stop