C8051F040-GQ Silicon Laboratories Inc, C8051F040-GQ Datasheet - Page 166
![IC 8051 MCU 64K FLASH 100TQFP](/photos/12/20/122007/c8051f040-gq_sml.jpg)
C8051F040-GQ
Manufacturer Part Number
C8051F040-GQ
Description
IC 8051 MCU 64K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Datasheets
1.C8051F040-TB.pdf
(328 pages)
2.C8051F040-TB.pdf
(2 pages)
3.C8051F043-GQ.pdf
(328 pages)
Specifications of C8051F040-GQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
100-TQFP, 100-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 13x12b; D/A 2x10b, 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
CAN/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
64
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F040DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 13-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
64
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
Rohs Compliant
Yes
Data Rom Size
64 KB
A/d Bit Size
12 bit
A/d Channels Available
13
Height
1 mm
Length
14 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
14 mm
Package
100TQFP
Device Core
8051
Family Name
C8051F04x
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1205 - DEV KIT FOR F040/F041/F042/F043
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1204
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F040-GQ
Manufacturer:
SiliconL
Quantity:
702
Company:
Part Number:
C8051F040-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F040-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F040-GQR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
- Current page: 166 of 328
- Download datasheet (3Mb)
C8051F040/1/2/3/4/5/6/7
13.1. Power-On Reset
The C8051F04x family incorporates a power supply monitor that holds the MCU in the reset state until V
rises above the V
the Electrical Characteristics of the power supply monitor circuit. The /RST pin is asserted low until the end
of the 100 ms V
enabled and disabled using the external V
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. All of the other
reset flags in the RSTSRC register are indeterminate. PORSF is cleared by all other resets. Since all
resets cause program execution to begin at the same location (0x0000), software can read the PORSF
flag to determine if a power-up was the cause of reset. The contents of internal data memory should be
assumed to be undefined after a power-on reset.
13.2. Power-Fail Reset
When a power-down transition or power irregularity causes V
monitor will drive the /RST pin low and return the CIP-51 to the reset state. When V
above V
Figure 13.2). Note that even though internal data memory contents are not altered by the power-fail reset,
it is impossible to determine if V
set to logic 1, the data may no longer be valid.
13.3. External Reset
The external /RST pin provides a means for external circuitry to force the MCU into a reset state. Asserting
the /RST pin low will cause the MCU to enter the reset state. It may be desirable to provide an external pul-
166
Logic HIGH
Logic LOW
RST
, the CIP-51 will leave the reset state in the same manner as that for the power-on reset (see
2.70
2.55
2.0
1.0
DD
RST
Monitor timeout in order to allow the V
/RST
level during power-up. See Figure 13.2 for timing diagram, and refer to Table 13.1 for
V
RST
DD
dropped below the level required for data retention. If the PORSF flag is
Figure 13.2. Reset Timing
Power-On Reset
DD
Reset Time
Delay
monitor enable pin (MONEN).
Rev. 1.5
DD
supply to stabilize. The V
DD
to drop below V
VDD Monitor Reset
Reset Time
Delay
RST
DD
, the power supply
DD
returns to a level
Monitor reset is
t
DD
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