C8051F040-GQ Silicon Laboratories Inc, C8051F040-GQ Datasheet - Page 205
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C8051F040-GQ
Manufacturer Part Number
C8051F040-GQ
Description
IC 8051 MCU 64K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Datasheets
1.C8051F040-TB.pdf
(328 pages)
2.C8051F040-TB.pdf
(2 pages)
3.C8051F043-GQ.pdf
(328 pages)
Specifications of C8051F040-GQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
100-TQFP, 100-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 13x12b; D/A 2x10b, 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
CAN/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
64
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F040DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 13-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
64
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
Rohs Compliant
Yes
Data Rom Size
64 KB
A/d Bit Size
12 bit
A/d Channels Available
13
Height
1 mm
Length
14 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
14 mm
Package
100TQFP
Device Core
8051
Family Name
C8051F04x
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1205 - DEV KIT FOR F040/F041/F042/F043
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1204
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F040-GQ
Manufacturer:
SiliconL
Quantity:
702
Company:
Part Number:
C8051F040-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F040-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F040-GQR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
17.1.1. Crossbar Pin Assignment and Allocation
The Crossbar assigns Port pins to a peripheral if the corresponding enable bits of the peripheral are set to
a logic 1 in the Crossbar configuration registers XBR0, XBR1, XBR2, and XBR3, shown in SFR Definition
17.1, SFR Definition 17.2, SFR Definition 17.3, and SFR Definition 17.4. For example, if the UART0EN bit
(XBR0.2) is set to a logic 1, the TX0 and RX0 pins will be mapped to P0.0 and P0.1 respectively. Because
UART0 has the highest priority, its pins will always be mapped to P0.0 and P0.1 when UART0EN is set to
a logic 1. If a digital peripheral’s enable bits are not set to a logic 1, then its ports are not accessible at the
Port pins of the device. Also note that the Crossbar assigns pins to all associated functions when a serial
communication peripheral is selected (i.e. SMBus, SPI, UART). It would be impossible, for example, to
assign TX0 to a Port pin without assigning RX0 as well. Each combination of enabled peripherals results in
a unique device pinout.
All Port pins on Ports 0 through 3 that are not allocated by the Crossbar can be accessed as General-Pur-
pose I/O (GPIO) pins by reading and writing the associated Port Data registers (See SFR Definition 17.5,
TX0
RX0
SCK
MISO
MOSI
NSS
SDA
SCL
TX1
RX1
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
CP0
CP1
CP2
T0
/INT0
T1
/INT1
T2
T2EX
T3
T3EX
T4
T4EX
/SYSCLK
CNVSTR0
CNVSTR2
PIN I/O 0
z
z
z
z
z
z z z z z z z z z z z z z z z z z
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z z z z z z z z z z z z z z z z z z z z z z
z z z z z z z z z z z z z z z z z z z z z z z
z z z z z z z z z z z z z z z z z z z z z z z z
z z z z z z z z z z z z z z z z z z z z z z z z z
z z z z z z z z z z z z z z z z z z z z z z z z z z
z z z z z z z z z z z z z z z z z z z z z z z z z z z
z z z z z z z z z z z z z z z z z z z z z z z z z z z z
z z z z z z z z z z z z z z z z z z z z z z z z z z z z z
z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z
z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z
z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z
z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z
z
z
z
z
z
1
z
z
z z z z z
z z z z z z z
z z z z z z z z z
z
2
z
z
z z z z z
z z z z z z z
z z z z z z z z z
z
3
P0
z
z z z z z z z z z
z
4
z
z z z z z z z z z
z
5
z z z z z z z z z
6
Figure 17.3. Priority Crossbar Decode Table
NSS is not assigned to a port pin when the SPI is placed in 3-wire mode
z z z z z z z z z
7
0
AIN1 Inputs/Non-muxed Addr H
1
2
(EMIFLE = 0; P1MDIN = 0xFF)
3
P1
4
5
6
7
Muxed Addr H/Non-muxed Addr L
0
Rev. 1.5
1
2
C8051F040/1/2/3/4/5/6/7
3
P2
4
5
6
7
0
Muxed Data/Non-muxed Data
1
2
3
P3
4
5
6
7
Crossbar Register Bits
UART0EN:
UART1EN:
CNVSTE0: XBR2.0
CNVSTE2: XBR3.2
SMB0EN:
PCA0ME:
SYSCKE: XBR1.7
SPI0EN:
T2EXE: XBR1.6
T3EXE: XBR3.1
T4EXE: XBR2.4
ECI0E: XBR0.6
INT0E: XBR1.2
INT1E: XBR1.4
CP0E: XBR0.7
CP1E: XBR1.0
CP2E: XBR3.3
T0E: XBR1.1
T1E: XBR1.3
T2E: XBR1.5
T3E: XBR3.0
T4E: XBR2.3
XBR0.2
XBR0.1
XBR0.0
XBR2.2
XBR0.[5:3]
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